Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
6a0fe9f8
Commit
6a0fe9f8
authored
Jan 13, 2017
by
Tom Levens
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Fixes and cleanup
Signed-off-by:
Tom Levens
<
tom.levens@cern.ch
>
parent
0b5cb429
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
25 additions
and
25 deletions
+25
-25
VME_CR_CSR_Space.vhd
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+8
-8
xvme64x_core.vhd
hdl/vme64x-core/rtl/xvme64x_core.vhd
+17
-17
No files found.
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @
6a0fe9f8
...
...
@@ -390,14 +390,14 @@ begin
end
process
;
bar_o
<=
s_reg_bar
(
7
downto
3
);
f0_ader_o
<=
s_
reg_ader
(
0
);
f1_ader_o
<=
s_
reg_ader
(
1
);
f2_ader_o
<=
s_
reg_ader
(
2
);
f3_ader_o
<=
s_
reg_ader
(
3
);
f4_ader_o
<=
s_
reg_ader
(
4
);
f5_ader_o
<=
s_
reg_ader
(
5
);
f6_ader_o
<=
s_
reg_ader
(
6
);
f7_ader_o
<=
s_
reg_ader
(
7
);
f0_ader_o
<=
s_
ader
(
0
)
when
s_ader
(
0
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f1_ader_o
<=
s_
ader
(
1
)
when
s_ader
(
1
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f2_ader_o
<=
s_
ader
(
2
)
when
s_ader
(
2
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f3_ader_o
<=
s_
ader
(
3
)
when
s_ader
(
3
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f4_ader_o
<=
s_
ader
(
4
)
when
s_ader
(
4
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f5_ader_o
<=
s_
ader
(
5
)
when
s_ader
(
5
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f6_ader_o
<=
s_
ader
(
6
)
when
s_ader
(
6
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
f7_ader_o
<=
s_
ader
(
7
)
when
s_ader
(
7
)(
ADER_DFSR
)
=
'0'
else
(
others
=>
'0'
);
module_enable_o
<=
s_reg_bit_reg
(
4
);
vme_sysfail_ena_o
<=
s_reg_bit_reg
(
6
);
module_reset_o
<=
s_reg_bit_reg
(
7
);
...
...
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @
6a0fe9f8
...
...
@@ -315,31 +315,31 @@ begin -- wrapper
master_o
.
adr
<=
adr_out
(
29
downto
0
)
&
"00"
;
dat_in
<=
master_i
.
dat
;
gen_
user_cr_csr
:
if
g_user_csr_ext
=
false
generate
gen_
int_user_csr
:
if
g_user_csr_ext
=
false
generate
U_User_CSR
:
VME_User_CSR
generic
map
(
g_wb_data_width
=>
g_wb_data_width
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
addr_i
=>
user_csr_addr
,
data_i
=>
user_csr_data_out
,
data_o
=>
user_csr_data_in
,
we_i
=>
user_csr_we
,
irq_vector_o
=>
irq_vector
,
irq_level_o
=>
irq_level
,
endian_o
=>
endian
,
time_i
=>
x"0000000000"
,
bytes_i
=>
x"0000"
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
addr_i
=>
user_csr_addr
,
data_i
=>
user_csr_data_out
,
data_o
=>
user_csr_data_in
,
we_i
=>
user_csr_we
,
irq_vector_o
=>
irq_vector
,
irq_level_o
=>
irq_level
,
endian_o
=>
endian
,
time_i
=>
x"0000000000"
,
bytes_i
=>
x"0000"
);
end
generate
;
gen_
no_user_cr_csr
:
if
g_user_csr_ext
=
true
generate
user_csr_data_in
<=
user_csr_data_i
;
gen_
ext_user_csr
:
if
g_user_csr_ext
=
true
generate
user_csr_data_in
<=
user_csr_data_i
;
end
generate
;
user_csr_addr_o
<=
user_csr_addr
;
user_csr_data_o
<=
user_csr_data_out
;
user_csr_we_o
<=
user_csr_we
;
user_csr_addr_o
<=
user_csr_addr
;
user_csr_data_o
<=
user_csr_data_out
;
user_csr_we_o
<=
user_csr_we
;
end
wrapper
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment