Skip to content

V
VME64x core
Commit ec0db743 authored by palvarez's avatar palvarez
Browse files
Options 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@100 665b4545-5c6b-4c24-801b-41150b02b44b
parent 008e7541
Hide whitespace changes
Inline Side-by-side
Showing with 26 additions and 1 deletion
HDL/VFC_ISE/VME64e_VFC.gise
View file @ ec0db743
......@@ -307,7 +307,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.lso"/>
......@@ -330,6 +332,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.bld"/>
......@@ -342,6 +345,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.pcf"/>
<outfile xil_pn:name="vme64xcore_top_reg_map.map"/>
......@@ -356,6 +362,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.ncd"/>
<outfile xil_pn:name="vme64xcore_top_reg.pad"/>
......@@ -371,6 +378,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.bgn"/>
<outfile xil_pn:name="vme64xcore_top_reg.bit"/>
......@@ -383,6 +391,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
......@@ -394,6 +403,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
......@@ -404,6 +414,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
......@@ -415,6 +426,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.tsi"/>
<outfile xil_pn:name="vme64xcore_top_reg.twr"/>
......@@ -424,6 +436,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>
......
HDL/VME64e_ActHDL_src/VME_bus.vhd
View file @ ec0db743
......@@ -1721,6 +1721,7 @@ begin
'0';
s_locAddr2e <= s_phase1addr(63 downto 8) & s_phase2addr(7 downto 0);
process(clk_i)
begin
if rising_edge(clk_i) then
......
HDL/VME64e_ActHDL_src/wb_dma.vhd
View file @ ec0db743
......@@ -91,6 +91,7 @@ architecture RTL of wb_dma is
signal sl_sel_we, m_sel_we, m_sel : std_logic_vector(c_sell -1 downto 0);
signal advance_m_adr, inc_m_adr : std_logic;
signal is_m_ack_index_top_m1 : std_logic;
signal s_adr_step : unsigned(7 downto 0);
begin
-------------------------------------------------------------------------------
process(clk_i)
......@@ -258,12 +259,22 @@ begin
end if;
end process;
-------------------------------------------------------------------------------
process()
begin
s_adr_step <= to_unsigned(1, s_adr_step'length);
if sl_sel_i = "11111111" then
s_adr_step <= to_unsigned(1, s_adr_step'length);
end process;
process(m_adr, sl_adr_i, latch_psize, inc_m_adr)
begin
if latch_psize = '1' then
nx_m_adr <= unsigned(sl_adr_i);
elsif inc_m_adr = '1' then
nx_m_adr <= m_adr + 1;
nx_m_adr <= m_adr + s_adr_step;
else
nx_m_adr <= m_adr;
end if;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment