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VME64x core
Commit 008e7541 authored by palvarez's avatar palvarez
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@99 665b4545-5c6b-4c24-801b-41150b02b44b
parent 8d5971ec
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Showing with 14 additions and 9 deletions
HDL/VFC_ISE/VME64e_VFC.gise
View file @ 008e7541
......@@ -322,11 +322,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1309442216" xil_pn:in_ck="1246737430911366229" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4228032853562161068" xil_pn:start_ts="1309442215">
<transform xil_pn:end_ts="1309453392" xil_pn:in_ck="1246737430911366229" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4228032853562161068" xil_pn:start_ts="1309453392">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309450364" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309450345">
<transform xil_pn:end_ts="1309453412" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309453392">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -338,7 +338,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_cs.ngc"/>
<outfile xil_pn:name="vme64xcore_top_reg_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309450433" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309450364">
<transform xil_pn:end_ts="1309453629" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309453412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -352,7 +352,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_summary.xml"/>
<outfile xil_pn:name="vme64xcore_top_reg_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1309450612" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309450433">
<transform xil_pn:end_ts="1309453794" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309453629">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -367,7 +367,7 @@
<outfile xil_pn:name="vme64xcore_top_reg_pad.txt"/>
<outfile xil_pn:name="vme64xcore_top_reg_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309450680" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309450612">
<transform xil_pn:end_ts="1309453863" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309453794">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -411,7 +411,7 @@
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1309450612" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309450593">
<transform xil_pn:end_ts="1309453794" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309453771">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -420,6 +420,12 @@
<outfile xil_pn:name="vme64xcore_top_reg.twr"/>
<outfile xil_pn:name="vme64xcore_top_reg.twx"/>
</transform>
<transform xil_pn:end_ts="1309453185" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1309453181">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>
</generated_project>
HDL/ucf/SFpga.ucf
View file @ 008e7541
......@@ -61,8 +61,6 @@ NET "VME_DATA_b[31]" LOC = W14;
#NET "VmeP0LvdsBunchClkIn_i" LOC = AE15;
#NET "VmeP0LvdsBunchClkOut_o" LOC = AF15;
#NET "VmeSysClk_ik" LOC = L8;
NET "VME_ADDR_b[1]" LOC = M24;
NET "VME_ADDR_b[2]" LOC = M21;
NET "VME_ADDR_b[3]" LOC = L21;
......@@ -132,7 +130,6 @@ NET "clk_i" LOC = AF14;
#NET "Si57x_ik" LOC = B12;
#NET "Si57x_ikn" LOC = A12;
# PlanAhead Generated IO constraints
NET "FpLed_onb8_5" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_DIR_o" IOSTANDARD = LVCMOS33;
......@@ -239,3 +236,5 @@ NET "FpLed_onb8_6" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/02/21
NET "clk_i" TNM_NET = clk_i;
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
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