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VME64x core
Commit dafbb793 authored by Tom Levens's avatar Tom Levens
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Repository cleanup 

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
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README.txt → README
View file @ dafbb793
==================================================
vme64x-core project
--------------------------------------------------
......@@ -35,3 +34,10 @@ Matthieu Cattin
`-- vfc -> Board specific software
`-- python -> Python programs
==================================================
Please send any questions or opinions to:
Developers: rok.stefanic@cosylab.com, ziga.kroflic@cosylab.com
OHWR list: vme64x-core@ohwr.org
hdl/DISCLAIMER.txt deleted 100644 → 0
View file @ 52d53744
Please send any questions or opinions to:
Developers: rok.stefanic@cosylab.com, ziga.kroflic@cosylab.com
OHWR list: vme64x-core@ohwr.org
\ No newline at end of file
hdl/boards/svec/SVEC.ucf deleted 100644 → 0
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NET "Reset" LOC = P24;
NET "VME_ADDR_DIR_o" LOC = N5;
NET "VME_ADDR_OE_N_o" LOC = N4;
NET "VME_AM_i[0]" LOC = AK2;
NET "VME_AM_i[1]" LOC = AE4;
NET "VME_AM_i[2]" LOC = AF4;
NET "VME_AM_i[3]" LOC = AF3;
NET "VME_AM_i[4]" LOC = AG3;
NET "VME_AM_i[5]" LOC = V8;
NET "VME_DATA_b[0]" LOC = AA10;
NET "VME_DATA_b[1]" LOC = AA9;
NET "VME_DATA_b[2]" LOC = AD7;
NET "VME_DATA_b[3]" LOC = AE7;
NET "VME_DATA_b[4]" LOC = Y9;
NET "VME_DATA_b[5]" LOC = Y8;
NET "VME_DATA_b[6]" LOC = AE6;
NET "VME_DATA_b[7]" LOC = AF6;
NET "VME_DATA_b[8]" LOC = W11;
NET "VME_DATA_b[9]" LOC = Y11;
NET "VME_DATA_b[10]" LOC = AE5;
NET "VME_DATA_b[11]" LOC = AG5;
NET "VME_DATA_b[12]" LOC = T7;
NET "VME_DATA_b[13]" LOC = T6;
NET "VME_DATA_b[14]" LOC = AA7;
NET "VME_DATA_b[15]" LOC = AA6;
NET "VME_DATA_b[16]" LOC = AC6;
NET "VME_DATA_b[17]" LOC = AD6;
NET "VME_DATA_b[18]" LOC = AH5;
NET "VME_DATA_b[19]" LOC = AK5;
NET "VME_DATA_b[20]" LOC = W10;
NET "VME_DATA_b[21]" LOC = W9;
NET "VME_DATA_b[22]" LOC = AB7;
NET "VME_DATA_b[23]" LOC = AB6;
NET "VME_DATA_b[24]" LOC = W7;
NET "VME_DATA_b[25]" LOC = W6;
NET "VME_DATA_b[26]" LOC = AJ4;
NET "VME_DATA_b[27]" LOC = AK4;
NET "VME_DATA_b[28]" LOC = T9;
NET "VME_DATA_b[29]" LOC = T8;
NET "VME_DATA_b[30]" LOC = AH3;
NET "VME_DATA_b[31]" LOC = AK3;
NET "VME_IACK_n_i" LOC = N1;
NET "VME_RETRY_OE_o" LOC = R4;
NET "VME_RETRY_n_o" LOC = AB2;
NET "VME_RST_n_i" LOC = P4;
#NET "VmeTck_i" LOC = D22;
#NET "VmeTdi_i" LOC = C21;
#NET "VmeTdo_o" LOC = B21;
#NET "VmeTms_i" LOC = D21;
NET "VME_WRITE_n_i" LOC = R1;
#NET "FpLed_onb8_5" LOC = U3;
#NET "FpLed_onb8_6" LOC = U4;
NET "VME_AS_n_i" LOC = P6;
NET "VME_BERR_o" LOC = R3;
#NET "VmeDDirVfcToVdme_o" LOC = L9;
NET "VME_DATA_DIR_o" LOC = P2;
NET "VME_IACKIN_n_i" LOC = P7;
NET "VME_IACKOUT_n_o" LOC = N3;
NET "VME_IRQ_n_o[0]" LOC = AG4;
NET "VME_IRQ_n_o[3]" LOC = N9;
NET "VME_IRQ_n_o[4]" LOC = AF2;
NET "VME_IRQ_n_o[5]" LOC = AH2;
NET "VME_IRQ_n_o[6]" LOC = R7;
#NET "VmeP0LvdsBunchClkIn_i" LOC = AE15;
#NET "VmeP0LvdsBunchClkOut_o" LOC = AF15;
#NET "VmeSysClk_ik" LOC = L8;
NET "VME_ADDR_b[1]" LOC = AE3;
NET "VME_ADDR_b[2]" LOC = AE1;
NET "VME_ADDR_b[3]" LOC = N8;
NET "VME_ADDR_b[4]" LOC = N7;
NET "VME_ADDR_b[5]" LOC = AC5;
NET "VME_ADDR_b[6]" LOC = AC4;
NET "VME_ADDR_b[7]" LOC = AD4;
NET "VME_ADDR_b[8]" LOC = AD3;
NET "VME_ADDR_b[9]" LOC = AB4;
NET "VME_ADDR_b[10]" LOC = AB3;
NET "VME_ADDR_b[11]" LOC = AD2;
NET "VME_ADDR_b[12]" LOC = AD1;
NET "VME_ADDR_b[13]" LOC = AC3;
NET "VME_ADDR_b[14]" LOC = AC1;
NET "VME_ADDR_b[15]" LOC = Y4;
NET "VME_ADDR_b[16]" LOC = Y3;
NET "VME_ADDR_b[17]" LOC = Y2;
NET "VME_ADDR_b[18]" LOC = Y1;
NET "VME_ADDR_b[19]" LOC = AA5;
NET "VME_ADDR_b[20]" LOC = AA4;
NET "VME_ADDR_b[21]" LOC = W3;
NET "VME_ADDR_b[22]" LOC = W1;
NET "VME_ADDR_b[23]" LOC = V2;
NET "VME_ADDR_b[24]" LOC = V1;
NET "VME_ADDR_b[25]" LOC = U5;
NET "VME_ADDR_b[26]" LOC = U4;
NET "VME_ADDR_b[27]" LOC = U3;
NET "VME_ADDR_b[28]" LOC = U1;
NET "VME_ADDR_b[29]" LOC = T4;
NET "VME_ADDR_b[30]" LOC = T3;
NET "VME_ADDR_b[31]" LOC = T2;
NET "VME_DATA_OE_N_o" LOC = P1;
NET "VME_DS_n_i[0]" LOC = Y7;
NET "VME_DS_n_i[1]" LOC = Y6;
NET "VME_DTACK_OE_o" LOC = T1;
NET "VME_DTACK_n_o" LOC = R5;
NET "VME_GA_i[5]" LOC = M6;
NET "VME_GA_i[0]" LOC = V7;
NET "VME_GA_i[1]" LOC = AH1;
NET "VME_GA_i[2]" LOC = AJ1;
NET "VME_GA_i[3]" LOC = V10;
NET "VME_GA_i[4]" LOC = V9;
NET "VME_IRQ_n_o[1]" LOC = AH4;
NET "VME_IRQ_n_o[2]" LOC = N10;
NET "VME_LWORD_n_b" LOC = M7;
NET "clk_i" LOC = V26;
# PlanAhead Generated IO constraints
#NET "FpLed_onb8_6" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/02/21
NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%;
# Add by Davide for debug
NET "leds[0]" LOC = AD27;
NET "leds[1]" LOC = AD26;
NET "leds[2]" LOC = AC28;
NET "leds[3]" LOC = AC27;
NET "leds[4]" LOC = AE27;
NET "leds[5]" LOC = AE30;
NET "leds[6]" LOC = AF28;
NET "leds[7]" LOC = AE28;
hdl/boards/svec/rtl/IRQ_Generator_Top.vhd deleted 100644 → 0
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--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: IRQ_Generator_Top.vhd
--______________________________________________________________________
-- Description: This block implement a IRQ_Generator both WB 32 or 64
-- data transfer bus width compatible.
-- Block diagram:
-- ____________________________________________
-- | |
-- | |
-- | __________ ______________ |
-- | | WB | | INT_COUNT | |
-- | | LOGIC | |______________| |
-- W | | | ______________ |
-- B | | | | FREQ | |
-- | | | |______________| |
-- S | | | ______________ |
-- I | | | | | |
-- G | | | | | |
-- N | | | | IRQ | |
-- A | | | |Generator.vhd | |
-- L | | | | | |
-- S | | | | | |
-- | | | | | |
-- | |__________| | | |
-- | | | |
-- | |______________| |
-- | |
-- | |
-- |____________________________________________|
--
-- INT_COUNT --> address: 0x000
-- FREQ --> address: 0x004
-- IRQ Generator: this component sends an Interrupt request (pulse) to the
-- IRQ Controller --> Necessary to test the board.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity IRQ_Generator_Top is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port ( -- IRQ_Generator
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
-- wb slave side
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0)
);
end IRQ_Generator_Top;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of IRQ_Generator_Top is
signal s_rst : std_logic;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic;
signal s_wea : std_logic;
signal s_stall : std_logic;
signal s_ack : std_logic;
signal s_en_Freq : std_logic;
component IRQ_generator is
port(
clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector(31 downto 0);
Int_Count_i : in std_logic_vector(31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector(31 downto 0)
);
end component IRQ_generator;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_rst <= not(rst_i);
s_wea <= we_i and cyc_i and stb_i and (not s_stall);
s_Int_Count_o1 <= s_data when (s_IntCount_sel = '1' and s_wea = '1')
else s_Int_Count_o;
s_Read_IntCount <= '1' when s_IntCount_sel = '1' and we_i = '0' and s_ack = '1'
else '0';
s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
------------------------------------------------------------------------------------
-- The INT_COUNT register and the INT_RATE register should be write/read both when
-- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added:
gen64 : if (g_wb_data_width = 64) generate
s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ;
s_IntCount_sel <= '1' when sel_i = "11110000" and unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when sel_i = "00001111" and unsigned(adr_i) = 0 else
'0';
end generate gen64;
gen32 : if (g_wb_data_width = 32) generate
s_data <= dat_i;
s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
s_FREQ when s_Freq_sel = '1' else
(others => '0');
s_IntCount_sel <= '1' when unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when unsigned(adr_i) = 1 else
'0';
end generate gen32;
---------------------------------------------------------------
-- this process generate the ack; PIPELINED mode!
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') then
s_ack <= '0';
else
s_ack <= cyc_i and stb_i and (not s_stall) ;
end if;
end if;
end process;
----------------------------------------------------------------
-- stall handler
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') or s_ack = '1' then
s_stall <= '1';
elsif cyc_i = '1' then
s_stall <= '0';
end if;
end if;
end process;
-- Reg INT_COUNT
INT_COUNT : Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_i
);
-- Reg FREQ
FREQ : Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => s_data_f,
do => s_FREQ,
clk_i => clk_i
);
-- IRQ Generator
Inst_IRQ_generator: IRQ_generator port map(
clk_i => clk_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => Int_Ack_i,
IRQ_o => Int_Req_o,
Int_Count_o => s_Int_Count_o
);
------------------------------------------------------------------
stall_o <= s_stall;
ack_o <= s_ack;
err_o <= '0';
rty_o <= '0';
dat_o <= s_data_o;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/IRQ_generator.vhd deleted 100644 → 0
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hdl/boards/svec/rtl/Manifest.py deleted 100644 → 0
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files=["IRQ_Generator_Top.vhd",
"IRQ_generator.vhd",
"ram_8bits.vhd",
"spram.vhd",
"TOP_LEVEL.vhd",
"WB_Bridge.vhd",
"xwb_ram.vhd",
"wishbone_pkg.vhd",
"genram_pkg.vhd"];
\ No newline at end of file
hdl/boards/svec/rtl/TOP_LEVEL.vhd deleted 100644 → 0
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hdl/boards/svec/rtl/WB_Bridge.vhd deleted 100644 → 0
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--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: WB_Bridge.vhd
--_____________________________________________________________________________
-- Description: Insert this block between the vme64x core and your WB Application
-- if you want use the Interrupter.
-- Indeed this component acts as a bridge between the vme64x core and your WB
-- Application, and implements the IRQ Generator that sends the Interrupt request
-- to the IRQ_Controller located in the vme64x core.
-- Remember that:
-- INT_COUNT register --> 0x00
-- INT_RATE register --> 0x04
-- These two address (byte address) are reserved; don't use these to access
-- your WB memory!
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity WB_Bridge is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
Port ( clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0));
end WB_Bridge;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of WB_Bridge is
signal s_cyc : std_logic;
signal s_m_cyc : std_logic;
signal s_stb : std_logic;
signal s_m_stb : std_logic;
signal s_WbAppl : std_logic;
signal s_IRQGen : std_logic;
signal s_ack_gen : std_logic;
signal s_err_gen : std_logic;
signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_wb_data_width - 1 downto 0);
component IRQ_Generator_Top is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0)
);
end component IRQ_Generator_Top;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
---------------------------------------------------------------------
-- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application
genIRQGen64 : if (g_wb_data_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64;
genIRQGen32 : if (g_wb_data_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0';
end generate genIRQGen32;
s_WbAppl <= not s_IRQGen;
---------------------------------------------------------------------
s_cyc <= cyc_i and s_IRQGen;
s_stb <= stb_i and s_IRQGen;
s_m_cyc <= cyc_i and s_WbAppl;
s_m_stb <= stb_i and s_WbAppl;
----------------------------------------------------------------------
ack_o <= s_ack_gen xor m_ack_i;
err_o <= s_err_gen xor m_err_i;
rty_o <= s_rty_gen xor m_rty_i;
----------------------------------------------------------------------
stall_o <= m_stall_i when s_WbAppl ='1' else
s_stall_gen;
dat_o <= m_dat_i when s_WbAppl ='1' else
s_data_o_gen;
----------------------------------------------------------------------
m_cyc_o <= s_m_cyc;
m_stb_o <= s_m_stb;
m_adr_o <= adr_i;
m_dat_o <= dat_i;
m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
Int_Ack_i => Int_Ack_i,
Int_Req_o => Int_Req_o,
cyc_i => s_cyc,
stb_i => s_stb,
adr_i => adr_i,
sel_i => sel_i,
we_i => we_i,
dat_i => dat_i,
ack_o => s_ack_gen,
err_o => s_err_gen,
rty_o => s_rty_gen,
stall_o => s_stall_gen,
dat_o => s_data_o_gen
);
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec/rtl/genram_pkg.vhd deleted 100644 → 0
View file @ 52d53744
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
constant c_SIZE : integer := 256;
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural ;
g_size : natural := 16 ;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo