Commit dafbb793 authored by Tom Levens's avatar Tom Levens

Repository cleanup

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 52d53744
==================================================
vme64x-core project
--------------------------------------------------
......@@ -35,3 +34,10 @@ Matthieu Cattin
`-- vfc -> Board specific software
`-- python -> Python programs
==================================================
Please send any questions or opinions to:
Developers: rok.stefanic@cosylab.com, ziga.kroflic@cosylab.com
OHWR list: vme64x-core@ohwr.org
Please send any questions or opinions to:
Developers: rok.stefanic@cosylab.com, ziga.kroflic@cosylab.com
OHWR list: vme64x-core@ohwr.org
\ No newline at end of file
NET "Reset" LOC = P24;
NET "VME_ADDR_DIR_o" LOC = N5;
NET "VME_ADDR_OE_N_o" LOC = N4;
NET "VME_AM_i[0]" LOC = AK2;
NET "VME_AM_i[1]" LOC = AE4;
NET "VME_AM_i[2]" LOC = AF4;
NET "VME_AM_i[3]" LOC = AF3;
NET "VME_AM_i[4]" LOC = AG3;
NET "VME_AM_i[5]" LOC = V8;
NET "VME_DATA_b[0]" LOC = AA10;
NET "VME_DATA_b[1]" LOC = AA9;
NET "VME_DATA_b[2]" LOC = AD7;
NET "VME_DATA_b[3]" LOC = AE7;
NET "VME_DATA_b[4]" LOC = Y9;
NET "VME_DATA_b[5]" LOC = Y8;
NET "VME_DATA_b[6]" LOC = AE6;
NET "VME_DATA_b[7]" LOC = AF6;
NET "VME_DATA_b[8]" LOC = W11;
NET "VME_DATA_b[9]" LOC = Y11;
NET "VME_DATA_b[10]" LOC = AE5;
NET "VME_DATA_b[11]" LOC = AG5;
NET "VME_DATA_b[12]" LOC = T7;
NET "VME_DATA_b[13]" LOC = T6;
NET "VME_DATA_b[14]" LOC = AA7;
NET "VME_DATA_b[15]" LOC = AA6;
NET "VME_DATA_b[16]" LOC = AC6;
NET "VME_DATA_b[17]" LOC = AD6;
NET "VME_DATA_b[18]" LOC = AH5;
NET "VME_DATA_b[19]" LOC = AK5;
NET "VME_DATA_b[20]" LOC = W10;
NET "VME_DATA_b[21]" LOC = W9;
NET "VME_DATA_b[22]" LOC = AB7;
NET "VME_DATA_b[23]" LOC = AB6;
NET "VME_DATA_b[24]" LOC = W7;
NET "VME_DATA_b[25]" LOC = W6;
NET "VME_DATA_b[26]" LOC = AJ4;
NET "VME_DATA_b[27]" LOC = AK4;
NET "VME_DATA_b[28]" LOC = T9;
NET "VME_DATA_b[29]" LOC = T8;
NET "VME_DATA_b[30]" LOC = AH3;
NET "VME_DATA_b[31]" LOC = AK3;
NET "VME_IACK_n_i" LOC = N1;
NET "VME_RETRY_OE_o" LOC = R4;
NET "VME_RETRY_n_o" LOC = AB2;
NET "VME_RST_n_i" LOC = P4;
#NET "VmeTck_i" LOC = D22;
#NET "VmeTdi_i" LOC = C21;
#NET "VmeTdo_o" LOC = B21;
#NET "VmeTms_i" LOC = D21;
NET "VME_WRITE_n_i" LOC = R1;
#NET "FpLed_onb8_5" LOC = U3;
#NET "FpLed_onb8_6" LOC = U4;
NET "VME_AS_n_i" LOC = P6;
NET "VME_BERR_o" LOC = R3;
#NET "VmeDDirVfcToVdme_o" LOC = L9;
NET "VME_DATA_DIR_o" LOC = P2;
NET "VME_IACKIN_n_i" LOC = P7;
NET "VME_IACKOUT_n_o" LOC = N3;
NET "VME_IRQ_n_o[0]" LOC = AG4;
NET "VME_IRQ_n_o[3]" LOC = N9;
NET "VME_IRQ_n_o[4]" LOC = AF2;
NET "VME_IRQ_n_o[5]" LOC = AH2;
NET "VME_IRQ_n_o[6]" LOC = R7;
#NET "VmeP0LvdsBunchClkIn_i" LOC = AE15;
#NET "VmeP0LvdsBunchClkOut_o" LOC = AF15;
#NET "VmeSysClk_ik" LOC = L8;
NET "VME_ADDR_b[1]" LOC = AE3;
NET "VME_ADDR_b[2]" LOC = AE1;
NET "VME_ADDR_b[3]" LOC = N8;
NET "VME_ADDR_b[4]" LOC = N7;
NET "VME_ADDR_b[5]" LOC = AC5;
NET "VME_ADDR_b[6]" LOC = AC4;
NET "VME_ADDR_b[7]" LOC = AD4;
NET "VME_ADDR_b[8]" LOC = AD3;
NET "VME_ADDR_b[9]" LOC = AB4;
NET "VME_ADDR_b[10]" LOC = AB3;
NET "VME_ADDR_b[11]" LOC = AD2;
NET "VME_ADDR_b[12]" LOC = AD1;
NET "VME_ADDR_b[13]" LOC = AC3;
NET "VME_ADDR_b[14]" LOC = AC1;
NET "VME_ADDR_b[15]" LOC = Y4;
NET "VME_ADDR_b[16]" LOC = Y3;
NET "VME_ADDR_b[17]" LOC = Y2;
NET "VME_ADDR_b[18]" LOC = Y1;
NET "VME_ADDR_b[19]" LOC = AA5;
NET "VME_ADDR_b[20]" LOC = AA4;
NET "VME_ADDR_b[21]" LOC = W3;
NET "VME_ADDR_b[22]" LOC = W1;
NET "VME_ADDR_b[23]" LOC = V2;
NET "VME_ADDR_b[24]" LOC = V1;
NET "VME_ADDR_b[25]" LOC = U5;
NET "VME_ADDR_b[26]" LOC = U4;
NET "VME_ADDR_b[27]" LOC = U3;
NET "VME_ADDR_b[28]" LOC = U1;
NET "VME_ADDR_b[29]" LOC = T4;
NET "VME_ADDR_b[30]" LOC = T3;
NET "VME_ADDR_b[31]" LOC = T2;
NET "VME_DATA_OE_N_o" LOC = P1;
NET "VME_DS_n_i[0]" LOC = Y7;
NET "VME_DS_n_i[1]" LOC = Y6;
NET "VME_DTACK_OE_o" LOC = T1;
NET "VME_DTACK_n_o" LOC = R5;
NET "VME_GA_i[5]" LOC = M6;
NET "VME_GA_i[0]" LOC = V7;
NET "VME_GA_i[1]" LOC = AH1;
NET "VME_GA_i[2]" LOC = AJ1;
NET "VME_GA_i[3]" LOC = V10;
NET "VME_GA_i[4]" LOC = V9;
NET "VME_IRQ_n_o[1]" LOC = AH4;
NET "VME_IRQ_n_o[2]" LOC = N10;
NET "VME_LWORD_n_b" LOC = M7;
NET "clk_i" LOC = V26;
# PlanAhead Generated IO constraints
#NET "FpLed_onb8_6" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/02/21
NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%;
# Add by Davide for debug
NET "leds[0]" LOC = AD27;
NET "leds[1]" LOC = AD26;
NET "leds[2]" LOC = AC28;
NET "leds[3]" LOC = AC27;
NET "leds[4]" LOC = AE27;
NET "leds[5]" LOC = AE30;
NET "leds[6]" LOC = AF28;
NET "leds[7]" LOC = AE28;
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: IRQ_Generator_Top.vhd
--______________________________________________________________________
-- Description: This block implement a IRQ_Generator both WB 32 or 64
-- data transfer bus width compatible.
-- Block diagram:
-- ____________________________________________
-- | |
-- | |
-- | __________ ______________ |
-- | | WB | | INT_COUNT | |
-- | | LOGIC | |______________| |
-- W | | | ______________ |
-- B | | | | FREQ | |
-- | | | |______________| |
-- S | | | ______________ |
-- I | | | | | |
-- G | | | | | |
-- N | | | | IRQ | |
-- A | | | |Generator.vhd | |
-- L | | | | | |
-- S | | | | | |
-- | | | | | |
-- | |__________| | | |
-- | | | |
-- | |______________| |
-- | |
-- | |
-- |____________________________________________|
--
-- INT_COUNT --> address: 0x000
-- FREQ --> address: 0x004
-- IRQ Generator: this component sends an Interrupt request (pulse) to the
-- IRQ Controller --> Necessary to test the board.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity IRQ_Generator_Top is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port ( -- IRQ_Generator
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
-- wb slave side
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0)
);
end IRQ_Generator_Top;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of IRQ_Generator_Top is
signal s_rst : std_logic;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic;
signal s_wea : std_logic;
signal s_stall : std_logic;
signal s_ack : std_logic;
signal s_en_Freq : std_logic;
component IRQ_generator is
port(
clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector(31 downto 0);
Int_Count_i : in std_logic_vector(31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector(31 downto 0)
);
end component IRQ_generator;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_rst <= not(rst_i);
s_wea <= we_i and cyc_i and stb_i and (not s_stall);
s_Int_Count_o1 <= s_data when (s_IntCount_sel = '1' and s_wea = '1')
else s_Int_Count_o;
s_Read_IntCount <= '1' when s_IntCount_sel = '1' and we_i = '0' and s_ack = '1'
else '0';
s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
------------------------------------------------------------------------------------
-- The INT_COUNT register and the INT_RATE register should be write/read both when
-- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added:
gen64 : if (g_wb_data_width = 64) generate
s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ;
s_IntCount_sel <= '1' when sel_i = "11110000" and unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when sel_i = "00001111" and unsigned(adr_i) = 0 else
'0';
end generate gen64;
gen32 : if (g_wb_data_width = 32) generate
s_data <= dat_i;
s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
s_FREQ when s_Freq_sel = '1' else
(others => '0');
s_IntCount_sel <= '1' when unsigned(adr_i) = 0 else
'0' ;
s_Freq_sel <= '1' when unsigned(adr_i) = 1 else
'0';
end generate gen32;
---------------------------------------------------------------
-- this process generate the ack; PIPELINED mode!
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') then
s_ack <= '0';
else
s_ack <= cyc_i and stb_i and (not s_stall) ;
end if;
end if;
end process;
----------------------------------------------------------------
-- stall handler
process(clk_i)
begin
if(rising_edge(clk_i)) then
if(s_rst = '0') or s_ack = '1' then
s_stall <= '1';
elsif cyc_i = '1' then
s_stall <= '0';
end if;
end if;
end process;
-- Reg INT_COUNT
INT_COUNT : Reg32bit
port map(
reset => s_rst,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_i
);
-- Reg FREQ
FREQ : Reg32bit
port map(
reset => s_rst,
enable => s_en_Freq,
di => s_data_f,
do => s_FREQ,
clk_i => clk_i
);
-- IRQ Generator
Inst_IRQ_generator: IRQ_generator port map(
clk_i => clk_i,
reset => s_rst,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => Int_Ack_i,
IRQ_o => Int_Req_o,
Int_Count_o => s_Int_Count_o
);
------------------------------------------------------------------
stall_o <= s_stall;
ack_o <= s_ack;
err_o <= '0';
rty_o <= '0';
dat_o <= s_data_o;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
This diff is collapsed.
files=["IRQ_Generator_Top.vhd",
"IRQ_generator.vhd",
"ram_8bits.vhd",
"spram.vhd",
"TOP_LEVEL.vhd",
"WB_Bridge.vhd",
"xwb_ram.vhd",
"wishbone_pkg.vhd",
"genram_pkg.vhd"];
\ No newline at end of file
This diff is collapsed.
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: WB_Bridge.vhd
--_____________________________________________________________________________
-- Description: Insert this block between the vme64x core and your WB Application
-- if you want use the Interrupter.
-- Indeed this component acts as a bridge between the vme64x core and your WB
-- Application, and implements the IRQ Generator that sends the Interrupt request
-- to the IRQ_Controller located in the vme64x core.
-- Remember that:
-- INT_COUNT register --> 0x00
-- INT_RATE register --> 0x04
-- These two address (byte address) are reserved; don't use these to access
-- your WB memory!
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity WB_Bridge is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
Port ( clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
Int_Req_o : out std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0));
end WB_Bridge;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of WB_Bridge is
signal s_cyc : std_logic;
signal s_m_cyc : std_logic;
signal s_stb : std_logic;
signal s_m_stb : std_logic;
signal s_WbAppl : std_logic;
signal s_IRQGen : std_logic;
signal s_ack_gen : std_logic;
signal s_err_gen : std_logic;
signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_wb_data_width - 1 downto 0);
component IRQ_Generator_Top is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0)
);
end component IRQ_Generator_Top;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
---------------------------------------------------------------------
-- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application
genIRQGen64 : if (g_wb_data_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64;
genIRQGen32 : if (g_wb_data_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0';
end generate genIRQGen32;
s_WbAppl <= not s_IRQGen;
---------------------------------------------------------------------
s_cyc <= cyc_i and s_IRQGen;
s_stb <= stb_i and s_IRQGen;
s_m_cyc <= cyc_i and s_WbAppl;
s_m_stb <= stb_i and s_WbAppl;
----------------------------------------------------------------------
ack_o <= s_ack_gen xor m_ack_i;
err_o <= s_err_gen xor m_err_i;
rty_o <= s_rty_gen xor m_rty_i;
----------------------------------------------------------------------
stall_o <= m_stall_i when s_WbAppl ='1' else
s_stall_gen;
dat_o <= m_dat_i when s_WbAppl ='1' else
s_data_o_gen;
----------------------------------------------------------------------
m_cyc_o <= s_m_cyc;
m_stb_o <= s_m_stb;
m_adr_o <= adr_i;
m_dat_o <= dat_i;
m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_i,
rst_i => rst_i,
Int_Ack_i => Int_Ack_i,
Int_Req_o => Int_Req_o,
cyc_i => s_cyc,
stb_i => s_stb,
adr_i => adr_i,
sel_i => sel_i,
we_i => we_i,
dat_i => dat_i,
ack_o => s_ack_gen,
err_o => s_err_gen,
rty_o => s_rty_gen,
stall_o => s_stall_gen,
dat_o => s_data_o_gen
);
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
package genram_pkg is
constant c_SIZE : integer := 256;
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural ;
g_size : natural := 16 ;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end genram_pkg;
--______________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________________
-- File: ram_8bits.vhd
--______________________________________________________________________________
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity ram_8bits is
generic (
size : integer := c_SIZE
);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
do : out std_logic_vector (7 downto 0);
we : in std_logic;
clk_i : in std_logic);
end ram_8bits;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of ram_8bits is
type t_ram_type is array(size-1 downto 0) of std_logic_vector(7 downto 0);
signal sram : t_ram_type;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (we = '1') then
sram(conv_integer(unsigned(addr))) <= di;
end if;
do <= sram(conv_integer(unsigned(addr)));
end if;
end process;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: spram.vhd
--______________________________________________________________________________
-- Description: single port ram with byte granularity
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity spram is
generic (
-- standard parameters
g_data_width : integer := c_wishbone_data_width;
g_size : integer := c_SIZE;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "read_first"; -- not used
g_init_file : string := "" -- not used
);
port (
clk_i : in std_logic; -- clock input
-- byte write enable
bwe_i : in std_logic_vector(((g_data_width)/8)-1 downto 0);
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end spram;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of spram is
constant c_num_bytes : integer := (g_data_width)/8;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(size => g_size)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
we => bwe_i(i),
clk_i => clk_i
);
end generate;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
This diff is collapsed.
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: xwb_ram.vhd
--______________________________________________________________________
-- Description: This block acts as WB Slave to test the vme64x interface
-- Block diagram:
-- ______________________
-- | |
-- | |
-- | __________ |
-- | | WB | |
-- | | LOGIC | |
-- W | | | |
-- B | | | |
-- | |__________| |
-- S | ______________ |
-- I | | | |
-- G | | | |
-- N | | RAM | |
-- A | | 64-bit port | |
-- L | | Byte | |
-- S | | Granularity | |
-- | | | |
-- | | | |
-- | | | |
-- | |______________| |
-- | |
-- | |
-- |______________________|
--
-- The RAM is a single port ram, 64 bit wide with byte granularity.
-- WB LOGIC: some processes add to generate the acknowledge and
-- the enable signals.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity xwb_ram is
generic(
g_size : integer := c_SIZE;
g_init_file : string := "";
g_must_have_init_file : boolean := false;
g_slave1_interface_mode : t_wishbone_interface_mode;
g_slave1_granularity : t_wishbone_address_granularity
);
port(
clk_sys_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
end xwb_ram;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture struct of xwb_ram is
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
signal s_wea : std_logic;
signal s_bwea : std_logic_vector(c_wishbone_data_width/8-1 downto 0);
signal slave1_out : t_wishbone_slave_out;
signal s_cyc : std_logic;
signal s_stb : std_logic;
signal s_rst : std_logic;
signal s_stall : std_logic;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
-- RAM memory
U_DPRAM : entity work.spram
generic map(
-- standard parameters
g_data_width => c_wishbone_data_width,
g_size => g_size,
g_with_byte_enable => true,
g_init_file => "",
g_addr_conflict_resolution => "read_first"
)
port map(
clk_i => clk_sys_i,
bwe_i => s_bwea,
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0),
d_i => slave1_i.dat,
q_o => slave1_o.dat
);
-- WB Logic:
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb and (not s_stall);
process(clk_sys_i)
begin
if(rising_edge(clk_sys_i)) then
if(slave1_out.ack = '1' and g_slave1_interface_mode = CLASSIC) then
slave1_out.ack <= '0';
else
slave1_out.ack <= slave1_i.cyc and slave1_i.stb and (not s_stall) ;
end if;
end if;
end process;
s_stall <= '0';
slave1_o.stall <= s_stall;
slave1_o.err <= '0'; --slave1_out.ack;
slave1_o.rty <= '0'; -- '0';
slave1_o.ack <= slave1_out.ack;
end struct;
--===========================================================================
-- Architecture end
--===========================================================================
files =["VME64x_Package.vhd",
"VME64x_SIM_Package.vhd",
"VME64x_TB.vhd",
"../../../../vme64x-core/rtl/VME64xCore_Top.vhd",
"../../../../vme64x-core/rtl/vme64x_pack.vhd",
"../../../../vme64x-core/rtl/VME_Access_Decode.vhd",
"../../../../vme64x-core/rtl/VME_Am_Match.vhd",
"../../../../vme64x-core/rtl/VME_bus.vhd",
"../../../../vme64x-core/rtl/VME_CR_CSR_Space.vhd",
"../../../../vme64x-core/rtl/VME_CR_pack.vhd",
"../../../../vme64x-core/rtl/VME_CSR_pack.vhd",
"../../../../vme64x-core/rtl/VME_CRAM.vhd",
"../../../../vme64x-core/rtl/VME_Funct_Match.vhd",
"../../../../vme64x-core/rtl/VME_Init.vhd",
"../../../../vme64x-core/rtl/VME_IRQ_Controller.vhd",
"../../../../vme64x-core/rtl/VME_SharedComps.vhd",
"../../../../vme64x-core/rtl/VME_swapper.vhd",
"../../../../vme64x-core/rtl/VME_Wb_master.vhd"];
modules = {"local":[ "../../rtl"]};
--------------------------------------------------------------------------------------
---------------------------VME64x_Package-----------------------------------------
--------------------------------------------------------------------------------------
-- Date : Fri Mar 03 2012
--
-- Author : Davide Pedretti
--
-- Company : CERN
--
-- Description : VME64x constants, records, type...
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;
use work.vme64x_pack.all;
package VME64x is
subtype Vme64xAddressType is std_logic_vector(31 downto 1); -- (31 downto 0)
subtype Vme64xDataType is std_logic_vector(31 downto 0);
subtype Vme64xAddressModType is std_logic_vector(5 downto 0);
type VME64xBusOut_Record is -- This is an output for the VME64x master
record
Vme64xAsN : std_logic;
Vme64xDs1N : std_logic;
Vme64xDs0N : std_logic;
Vme64xLWORDN : std_logic;
Vme64xIACK : std_logic;
Vme64xIACKIN : std_logic;
Vme64xWRITEN : std_logic;
Vme64xAM : Vme64xAddressModType;
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
end record;
type VME64xBusIn_Record is -- This is an input for the VME64x master
record
Vme64xDtackN : std_logic;
Vme64xBerrN : std_logic;
Vme64xRetryN : std_logic;
Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType;
Vme64xLWORDN : std_logic;
Vme64xIACKOUT : std_logic;
Vme64xIRQ : std_logic_vector(6 downto 0);
end record;
-- Types
type t_Buffer_BLT is array (0 to 66) of std_logic_vector(31 downto 0); -- for BLT transfer
--The buffer has 65 positions, not 64; the last position is for test the error if i transfer more of 256 bytes.
type t_Buffer_MBLT is array (0 to 258) of std_logic_vector(63 downto 0); -- for MBLT transfer
--The buffer has 258 positions, not 256; the last position is for test the error if i transfer more of 256 bytes.
type t_dataTransferType is (D08Byte0, D08Byte1, D08Byte2, D08Byte3, D16Byte01, D16Byte23, D32); -- for D64 use dataTransferType D32!
type t_Addressing_Type is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK,
A64, A64_BLT, A64_MBLT, A64_LCK, A32_2eVME, A64_2eVME, A32_2eSST, A64_2eSST, error);
-- Declare constants
-- constant <constant_name> : time := <time_unit> ns;
constant BA : std_logic_vector(7 downto 0) := "11110000";
constant VME_GA : std_logic_vector(5 downto 0) := "110111"; -- GA parity match '1' & slot number
constant ID_Master : std_logic_vector(7 downto 0) := "00001111"; -- max 31
constant ADER0_A16_S : std_logic_vector(31 downto 0) := "0000000000000000" & BA(7 downto 3) & "000" & c_A16 &"00";
constant ADER0_A24_S : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_S &"00";
constant ADER0_A24_BLT : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_BLT &"00";
constant ADER0_A24_MBLT : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_MBLT &"00";
constant ADER0_A32 : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32 &"00";
constant ADER0_A32_BLT : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32_BLT &"00";
constant ADER0_A32_MBLT : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000000000000000" & c_A32_MBLT &"00";
constant ADER1_A64 : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64 &"00";
constant ADER1_A64_BLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_BLT &"00";
constant ADER1_A64_MBLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_MBLT &"00";
constant ADER1_A64_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
constant ADER2_A32_2eVME : std_logic_vector(31 downto 0) := BA(7 downto 3) & "00000000000000000" & x"01" &"01";
constant ADER2_A64_2eVME : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"02" &"01";
constant ADER2_A32_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"11" &"01";
constant ADER2_A64_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"12" &"01";
constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
-- CSR constants
constant c_BAR : std_logic_vector := x"7FFFF";
constant c_BIT_SET_REG : std_logic_vector := x"7FFFB";
constant c_BIT_CLR_REG : std_logic_vector := x"7FFF7";
constant c_CRAM_OWNER : std_logic_vector := x"7FFF3";
constant c_USR_BIT_SET_REG : std_logic_vector := x"7FFEF";
constant c_USR_BIT_CLR_REG : std_logic_vector := x"7FFEB";
constant c_FUNC7_ADER_0 : std_logic_vector := x"7FFDF";
constant c_FUNC7_ADER_1 : std_logic_vector := x"7FFDB";
constant c_FUNC7_ADER_2 : std_logic_vector := x"7FFD7";
constant c_FUNC7_ADER_3 : std_logic_vector := x"7FFD3";
constant c_FUNC6_ADER_0 : std_logic_vector := x"7FFCF";
constant c_FUNC6_ADER_1 : std_logic_vector := x"7FFCB";
constant c_FUNC6_ADER_2 : std_logic_vector := x"7FFC7";
constant c_FUNC6_ADER_3 : std_logic_vector := x"7FFC3";
constant c_FUNC5_ADER_0 : std_logic_vector := x"7FFBF";
constant c_FUNC5_ADER_1 : std_logic_vector := x"7FFBB";
constant c_FUNC5_ADER_2 : std_logic_vector := x"7FFB7";
constant c_FUNC5_ADER_3 : std_logic_vector := x"7FFB3";
constant c_FUNC4_ADER_0 : std_logic_vector := x"7FFAF";
constant c_FUNC4_ADER_1 : std_logic_vector := x"7FFAB";
constant c_FUNC4_ADER_2 : std_logic_vector := x"7FFA7";
constant c_FUNC4_ADER_3 : std_logic_vector := x"7FFA3";
constant c_FUNC3_ADER_0 : std_logic_vector := x"7FF9F";
constant c_FUNC3_ADER_1 : std_logic_vector := x"7FF9B";
constant c_FUNC3_ADER_2 : std_logic_vector := x"7FF97";
constant c_FUNC3_ADER_3 : std_logic_vector := x"7FF93";
constant c_FUNC2_ADER_0 : std_logic_vector := x"7FF8F";
constant c_FUNC2_ADER_1 : std_logic_vector := x"7FF8B";
constant c_FUNC2_ADER_2 : std_logic_vector := x"7FF87";
constant c_FUNC2_ADER_3 : std_logic_vector := x"7FF83";
constant c_FUNC1_ADER_0 : std_logic_vector := x"7FF7F";
constant c_FUNC1_ADER_1 : std_logic_vector := x"7FF7B";
constant c_FUNC1_ADER_2 : std_logic_vector := x"7FF77";
constant c_FUNC1_ADER_3 : std_logic_vector := x"7FF73";
constant c_FUNC0_ADER_0 : std_logic_vector := x"7FF6F";
constant c_FUNC0_ADER_1 : std_logic_vector := x"7FF6B";
constant c_FUNC0_ADER_2 : std_logic_vector := x"7FF67";
constant c_FUNC0_ADER_3 : std_logic_vector := x"7FF63";
constant c_BYTES0 : std_logic_vector := x"7FF3b";
constant c_MBLT_Endian : std_logic_vector := x"7Ff53";
constant c_IRQ_Vector : std_logic_vector := x"7FF5F";
constant c_IRQ_level : std_logic_vector := x"7FF5B";
constant c_WB32or64 : std_logic_vector := x"7FF33";
-- CR constant
constant c_StartDefinedCR : std_logic_vector := x"00000";
constant c_EndDefinedCR : std_logic_vector := x"00FFF";
end VME64x;
package body VME64x is
end VME64x;
This diff is collapsed.
This diff is collapsed.
vlib work
make
vsim -t 1ps -L unisim -c work.vme64x_tb
do wave1.do
run 100us
\ No newline at end of file
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group Top /vme64x_tb/uut/clk_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/Reset
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_AS_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_RST_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_WRITE_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_AM_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DS_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_GA_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_BERR_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DTACK_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_RETRY_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_LWORD_n_b
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_ADDR_b
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DATA_b
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IRQ_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IACKIN_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IACKOUT_n_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_IACK_n_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_RETRY_OE_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DTACK_OE_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DATA_DIR_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_DATA_OE_N_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_ADDR_DIR_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/VME_ADDR_OE_N_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/leds
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbDat_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbDat_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbAdr_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbCyc_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbErr_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbRty_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbSel_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbStb_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbAck_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbWe_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbStall_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbIrq_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemDat_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemDat_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemAdr_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemCyc_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemErr_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemRty_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemSel_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemStb_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemAck_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemWe_i
add wave -noupdate -expand -group Top /vme64x_tb/uut/WbMemStall_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/clk_in_buf
add wave -noupdate -expand -group Top /vme64x_tb/uut/clk_in
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_locked
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_fb
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_INT_ack
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_rst_n
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_DATA_b_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_DATA_DIR
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_ADDR_DIR
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_ADDR_b_o
add wave -noupdate -expand -group Top /vme64x_tb/uut/s_VME_LWORD_n_b_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8963000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {97409 ns} {100137 ns}
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NET "Reset" LOC = P24;
NET "VME_ADDR_DIR_o" LOC = N5;
NET "VME_ADDR_OE_N_o" LOC = N4;
NET "VME_AM_i[0]" LOC = AK2;
NET "VME_AM_i[1]" LOC = AE4;
NET "VME_AM_i[2]" LOC = AF4;
NET "VME_AM_i[3]" LOC = AF3;
NET "VME_AM_i[4]" LOC = AG3;
NET "VME_AM_i[5]" LOC = V8;
NET "VME_DATA_b[0]" LOC = AA10;
NET "VME_DATA_b[1]" LOC = AA9;
NET "VME_DATA_b[2]" LOC = AD7;
NET "VME_DATA_b[3]" LOC = AE7;
NET "VME_DATA_b[4]" LOC = Y9;
NET "VME_DATA_b[5]" LOC = Y8;
NET "VME_DATA_b[6]" LOC = AE6;
NET "VME_DATA_b[7]" LOC = AF6;
NET "VME_DATA_b[8]" LOC = W11;
NET "VME_DATA_b[9]" LOC = Y11;
NET "VME_DATA_b[10]" LOC = AE5;
NET "VME_DATA_b[11]" LOC = AG5;
NET "VME_DATA_b[12]" LOC = T7;
NET "VME_DATA_b[13]" LOC = T6;
NET "VME_DATA_b[14]" LOC = AA7;
NET "VME_DATA_b[15]" LOC = AA6;
NET "VME_DATA_b[16]" LOC = AC6;
NET "VME_DATA_b[17]" LOC = AD6;
NET "VME_DATA_b[18]" LOC = AH5;
NET "VME_DATA_b[19]" LOC = AK5;
NET "VME_DATA_b[20]" LOC = W10;
NET "VME_DATA_b[21]" LOC = W9;
NET "VME_DATA_b[22]" LOC = AB7;
NET "VME_DATA_b[23]" LOC = AB6;
NET "VME_DATA_b[24]" LOC = W7;
NET "VME_DATA_b[25]" LOC = W6;
NET "VME_DATA_b[26]" LOC = AJ4;
NET "VME_DATA_b[27]" LOC = AK4;
NET "VME_DATA_b[28]" LOC = T9;
NET "VME_DATA_b[29]" LOC = T8;
NET "VME_DATA_b[30]" LOC = AH3;
NET "VME_DATA_b[31]" LOC = AK3;
NET "VME_IACK_n_i" LOC = N1;
NET "VME_RETRY_OE_o" LOC = R4;
NET "VME_RETRY_n_o" LOC = AB2;
NET "VME_RST_n_i" LOC = P4;
#NET "VmeTck_i" LOC = D22;
#NET "VmeTdi_i" LOC = C21;
#NET "VmeTdo_o" LOC = B21;
#NET "VmeTms_i" LOC = D21;
NET "VME_WRITE_n_i" LOC = R1;
#NET "FpLed_onb8_5" LOC = U3;
#NET "FpLed_onb8_6" LOC = U4;
NET "VME_AS_n_i" LOC = P6;
NET "VME_BERR_o" LOC = R3;
#NET "VmeDDirVfcToVdme_o" LOC = L9;
NET "VME_DATA_DIR_o" LOC = P2;
NET "VME_IACKIN_n_i" LOC = P7;
NET "VME_IACKOUT_n_o" LOC = N3;
NET "VME_IRQ_n_o[0]" LOC = AG4;
NET "VME_IRQ_n_o[3]" LOC = N9;
NET "VME_IRQ_n_o[4]" LOC = AF2;
NET "VME_IRQ_n_o[5]" LOC = AH2;
NET "VME_IRQ_n_o[6]" LOC = R7;
#NET "VmeP0LvdsBunchClkIn_i" LOC = AE15;
#NET "VmeP0LvdsBunchClkOut_o" LOC = AF15;
#NET "VmeSysClk_ik" LOC = L8;
NET "VME_ADDR_b[1]" LOC = AE3;
NET "VME_ADDR_b[2]" LOC = AE1;
NET "VME_ADDR_b[3]" LOC = N8;
NET "VME_ADDR_b[4]" LOC = N7;
NET "VME_ADDR_b[5]" LOC = AC5;
NET "VME_ADDR_b[6]" LOC = AC4;
NET "VME_ADDR_b[7]" LOC = AD4;
NET "VME_ADDR_b[8]" LOC = AD3;
NET "VME_ADDR_b[9]" LOC = AB4;
NET "VME_ADDR_b[10]" LOC = AB3;
NET "VME_ADDR_b[11]" LOC = AD2;
NET "VME_ADDR_b[12]" LOC = AD1;
NET "VME_ADDR_b[13]" LOC = AC3;
NET "VME_ADDR_b[14]" LOC = AC1;
NET "VME_ADDR_b[15]" LOC = Y4;
NET "VME_ADDR_b[16]" LOC = Y3;
NET "VME_ADDR_b[17]" LOC = Y2;
NET "VME_ADDR_b[18]" LOC = Y1;
NET "VME_ADDR_b[19]" LOC = AA5;
NET "VME_ADDR_b[20]" LOC = AA4;
NET "VME_ADDR_b[21]" LOC = W3;
NET "VME_ADDR_b[22]" LOC = W1;
NET "VME_ADDR_b[23]" LOC = V2;
NET "VME_ADDR_b[24]" LOC = V1;
NET "VME_ADDR_b[25]" LOC = U5;
NET "VME_ADDR_b[26]" LOC = U4;
NET "VME_ADDR_b[27]" LOC = U3;
NET "VME_ADDR_b[28]" LOC = U1;
NET "VME_ADDR_b[29]" LOC = T4;
NET "VME_ADDR_b[30]" LOC = T3;
NET "VME_ADDR_b[31]" LOC = T2;
NET "VME_DATA_OE_N_o" LOC = P1;
NET "VME_DS_n_i[0]" LOC = Y7;
NET "VME_DS_n_i[1]" LOC = Y6;
NET "VME_DTACK_OE_o" LOC = T1;
NET "VME_DTACK_n_o" LOC = R5;
NET "VME_GA_i[5]" LOC = M6;
NET "VME_GA_i[0]" LOC = V7;
NET "VME_GA_i[1]" LOC = AH1;
NET "VME_GA_i[2]" LOC = AJ1;
NET "VME_GA_i[3]" LOC = V10;
NET "VME_GA_i[4]" LOC = V9;
NET "VME_IRQ_n_o[1]" LOC = AH4;
NET "VME_IRQ_n_o[2]" LOC = N10;
NET "VME_LWORD_n_b" LOC = M7;
NET "clk_i" LOC = V26;
# PlanAhead Generated IO constraints
#NET "FpLed_onb8_6" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/02/21
NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%;
# Add by Davide for debug
NET "leds[0]" LOC = AD27;
NET "leds[1]" LOC = AD26;
NET "leds[2]" LOC = AC28;
NET "leds[3]" LOC = AC27;
NET "leds[4]" LOC = AE27;
NET "leds[5]" LOC = AE30;
NET "leds[6]" LOC = AF28;
NET "leds[7]" LOC = AE28;
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-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-- 2012-03-13 1.1 wterpstra Added initial value as array
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 1024;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram;
architecture syn of generic_dpram is
component generic_dpram_sameclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_init_value : t_generic_ram_init;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram_dualclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_init_value : t_generic_ram_init;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
gen_single_clk : if(g_dual_clock = false) generate
U_RAM_SC: generic_dpram_sameclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_init_value => g_init_value,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clk_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_single_clk;
gen_dual_clk : if(g_dual_clock = true) generate
U_RAM_DC: generic_dpram_dualclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_init_value => g_init_value,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
clkb_i => clkb_i,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_dual_clk;
end syn;
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library ieee;
use ieee.std_logic_1164.all;
--use work.genram_pkg.all;
--use work.common_components.all;
--library wbgen2;
use work.wbgen2_pkg.all;
entity wbgen2_dpssram is
generic (
g_data_width : natural := 32;
g_size : natural := 1024;
g_addr_width : natural := 10;
g_dual_clock : boolean := false;
g_use_bwsel : boolean := true);
port (
clk_a_i : in std_logic;
clk_b_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_width-1 downto 0);
addr_b_i : in std_logic_vector(g_addr_width-1 downto 0);
data_a_i : in std_logic_vector(g_data_width-1 downto 0);
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic
);
end wbgen2_dpssram;
architecture syn of wbgen2_dpssram is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
wrapped_dpram: generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_use_bwsel,
g_dual_clock => g_dual_clock)
port map (
rst_n_i => '1',
clka_i => clk_a_i,
bwea_i => bwsel_a_i,
wea_i => wr_a_i,
aa_i => addr_a_i,
da_i => data_a_i,
qa_o => data_a_o,
clkb_i => clk_b_i,
bweb_i => bwsel_b_i,
web_i => wr_b_i,
ab_i => addr_b_i,
db_i => data_b_i,
qb_o => data_b_o);
end syn;
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File mode changed from 100755 to 100644
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import pyvmelib
map = pyvmelib.Mapping(am=0x2f, base_address=0xXXXXXX, data_width=16, size=0x10000)
value = map.read(offset=0x3, width=8)[0]
print hex(value)
map.write(offset=0x3, width=8, values=0xa5)
map.write(offset=0x3, width=8, values=[0xa5, 0xff])
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