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VME64x core
Commit c84ccb71 authored by palvarez's avatar palvarez
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git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@101 665b4545-5c6b-4c24-801b-41150b02b44b
parent ec0db743
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Showing with 154 additions and 183 deletions
HDL/VFC_ISE/VME64e_VFC.gise
View file @ c84ccb71
......@@ -170,7 +170,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309160466" xil_pn:in_ck="5292202920342099773" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1309160466">
<transform xil_pn:end_ts="1309792465" xil_pn:in_ck="5292202920342099773" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1309792465">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
......@@ -222,7 +222,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309160466" xil_pn:in_ck="5292202920342099773" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1309160466">
<transform xil_pn:end_ts="1309792466" xil_pn:in_ck="5292202920342099773" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1309792465">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
......@@ -263,7 +263,7 @@
<outfile xil_pn:name="/ohr/ddr3-sp6-core/trunk/hdl/rtl/core-gen/memc5_infrastructure.vhd"/>
<outfile xil_pn:name="/ohr/ddr3-sp6-core/trunk/hdl/rtl/core-gen/memc5_wrapper.vhd"/>
</transform>
<transform xil_pn:end_ts="1309160470" xil_pn:in_ck="5292202920342099773" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1309160466">
<transform xil_pn:end_ts="1309792469" xil_pn:in_ck="5292202920342099773" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="889151390353550919" xil_pn:start_ts="1309792466">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
......@@ -303,13 +303,11 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309450345" xil_pn:in_ck="-4386731544833275205" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7631510052154532617" xil_pn:start_ts="1309450232">
<transform xil_pn:end_ts="1309793228" xil_pn:in_ck="-4386731544833275205" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7631510052154532617" xil_pn:start_ts="1309793144">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.lso"/>
......@@ -324,15 +322,14 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1309453392" xil_pn:in_ck="1246737430911366229" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4228032853562161068" xil_pn:start_ts="1309453392">
<transform xil_pn:end_ts="1309788602" xil_pn:in_ck="1246737430911366229" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4228032853562161068" xil_pn:start_ts="1309788602">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1309453412" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309453392">
<transform xil_pn:end_ts="1309793246" xil_pn:in_ck="1991227451224517426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5973292016675018579" xil_pn:start_ts="1309793228">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.bld"/>
......@@ -341,13 +338,10 @@
<outfile xil_pn:name="vme64xcore_top_reg_cs.ngc"/>
<outfile xil_pn:name="vme64xcore_top_reg_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309453629" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309453412">
<transform xil_pn:end_ts="1309793417" xil_pn:in_ck="-8441102077107081157" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1824173063049107586" xil_pn:start_ts="1309793246">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.pcf"/>
<outfile xil_pn:name="vme64xcore_top_reg_map.map"/>
......@@ -358,11 +352,10 @@
<outfile xil_pn:name="vme64xcore_top_reg_summary.xml"/>
<outfile xil_pn:name="vme64xcore_top_reg_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1309453794" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309453629">
<transform xil_pn:end_ts="1309793591" xil_pn:in_ck="3353801450926630214" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="2881300017542290041" xil_pn:start_ts="1309793417">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.ncd"/>
<outfile xil_pn:name="vme64xcore_top_reg.pad"/>
......@@ -374,11 +367,10 @@
<outfile xil_pn:name="vme64xcore_top_reg_pad.txt"/>
<outfile xil_pn:name="vme64xcore_top_reg_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1309453863" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309453794">
<transform xil_pn:end_ts="1309793666" xil_pn:in_ck="-6139244621610154419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="2321585675605421658" xil_pn:start_ts="1309793597">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.bgn"/>
<outfile xil_pn:name="vme64xcore_top_reg.bit"/>
......@@ -391,7 +383,6 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
......@@ -403,7 +394,6 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
......@@ -414,7 +404,6 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
......@@ -422,11 +411,10 @@
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1309453794" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309453771">
<transform xil_pn:end_ts="1309793591" xil_pn:in_ck="-6179112853177871454" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="5478904096812716945" xil_pn:start_ts="1309793570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="vme64xcore_top_reg.tsi"/>
<outfile xil_pn:name="vme64xcore_top_reg.twr"/>
......@@ -436,8 +424,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
</transforms>
......
HDL/VFC_ISE/VME64e_VFC.xise
View file @ c84ccb71
......@@ -445,8 +445,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vme64xcore_top_reg_tb/stimulGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.sim_vme64master" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vme64xcore_top_reg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.vme64xcore_top_reg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.vme64xcore_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -470,7 +470,7 @@
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.sim_vme64master" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.vme64xcore_top_reg_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.vme64xcore_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
HDL/VFC_ISE/VMEScope.cdc
View file @ c84ccb71
#ChipScope Core Inserter Project File Version 3.0
#Thu Jun 30 17:13:33 CEST 2011
#Mon Jul 04 17:14:17 CEST 2011
Project.device.designInputFile=/ohr/vme64x-core/trunk/HDL/VFC_ISE/vme64xcore_top_reg_cs.ngc
Project.device.designOutputFile=/ohr/vme64x-core/trunk/HDL/VFC_ISE/vme64xcore_top_reg_cs.ngc
Project.device.deviceFamily=18
......@@ -7,25 +7,25 @@ Project.device.enableRPMs=true
Project.device.outputDirectory=/ohr/vme64x-core/trunk/HDL/VFC_ISE/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*clk*
Project.filter<10>=*count*
Project.filter<11>=*beat*
Project.filter<12>=*wb_dma*
Project.filter<13>=*stb*
Project.filter<14>=*DS1*
Project.filter<15>=*Ds1pulse*
Project.filter<16>=*Dspulse*
Project.filter<17>=*data*
Project.filter<18>=*m_ac*
Project.filter<1>=
Project.filter<2>=s_clk
Project.filter<3>=s_clki
Project.filter<4>=*DS*
Project.filter<5>=*m_sel*
Project.filter<6>=*sel*
Project.filter<7>=*addr*
Project.filter<8>=*pulse*
Project.filter<9>=*size*
Project.filter<0>=*
Project.filter<10>=*size*
Project.filter<11>=*count*
Project.filter<12>=*beat*
Project.filter<13>=*wb_dma*
Project.filter<14>=*stb*
Project.filter<15>=*DS1*
Project.filter<16>=*Ds1pulse*
Project.filter<17>=*Dspulse*
Project.filter<18>=*data*
Project.filter<1>=*sel*
Project.filter<2>=*m_sel*
Project.filter<3>=
Project.filter<4>=*clk*
Project.filter<5>=s_clk
Project.filter<6>=s_clki
Project.filter<7>=*DS*
Project.filter<8>=*addr*
Project.filter<9>=*pulse*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
......@@ -372,10 +372,10 @@ Project.unit<0>.triggerChannel<10><8>=UUT/s_WBdataOut<8>
Project.unit<0>.triggerChannel<10><9>=UUT/s_WBdataOut<9>
Project.unit<0>.triggerChannel<11><0>=UUT/Uwb_dma/m_sel<1>
Project.unit<0>.triggerChannel<11><1>=UUT/Uwb_dma/m_sel<2>
Project.unit<0>.triggerChannel<11><2>=UUT/Uwb_dma/m_sel<3>
Project.unit<0>.triggerChannel<11><2>=VME_DS_n_i_1_IBUF
Project.unit<0>.triggerChannel<11><3>=UUT/Uwb_dma/m_sel<4>
Project.unit<0>.triggerChannel<11><4>=UUT/Uwb_dma/m_sel_we<4>
Project.unit<0>.triggerChannel<11><5>=UUT/Uwb_dma/m_sel_we<3>
Project.unit<0>.triggerChannel<11><5>=VME_DS_n_i_0_IBUF
Project.unit<0>.triggerChannel<11><6>=UUT/Uwb_dma/m_sel_we<2>
Project.unit<0>.triggerChannel<11><7>=UUT/Uwb_dma/m_sel_we<1>
Project.unit<0>.triggerChannel<12><0>=UUT/Uwb_dma/m_adr_o<7>
......@@ -563,6 +563,8 @@ Project.unit<0>.triggerPortIsData<10>=true
Project.unit<0>.triggerPortIsData<11>=false
Project.unit<0>.triggerPortIsData<12>=true
Project.unit<0>.triggerPortIsData<13>=true
Project.unit<0>.triggerPortIsData<14>=false
Project.unit<0>.triggerPortIsData<15>=false
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortIsData<3>=true
......
HDL/VFC_dev/VME64xCore_NoIpTop.vhd
View file @ c84ccb71
......@@ -269,6 +269,7 @@ architecture RTL of VME64xCore_Top is
signal s_transfer_done : std_logic;
signal sel_we : std_logic;
signal s_VME_ADDR_DIR : std_logic;
signal s_locAddr64 : std_logic_vector(63 downto 0);
begin
-- Uncomment this section for use of external CR and CRAM
......@@ -360,10 +361,10 @@ begin
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
sel_we <= not s_RW;
s_locAddr64 <= "000"&s_locAddr(63 downto 3);
Uwb_dma : wb_dma
generic map(c_dl => s_WBdataIn'length,
c_al => s_locAddr'length,
c_al => s_locAddr64'length,
c_sell => s_WBsel'length,
c_psizel => s_psize'length)
......@@ -376,7 +377,7 @@ begin
-- Slave WB with dma support
sl_dat_i => s_WBdataIn,
sl_dat_o => s_WBdataOut,
sl_adr_i => s_locAddr,
sl_adr_i => s_locAddr64,
sl_cyc_i => s_cyc,
sl_err_o => s_err,
sl_lock_i => s_lock,
......
HDL/VME64e_ActHDL_src/VME_bus.vhd
View file @ c84ccb71
This diff is collapsed.
HDL/VME64e_ActHDL_src/wb_dma.vhd
View file @ c84ccb71
......@@ -28,7 +28,7 @@ entity wb_dma is
c_psizel : integer := 10);
port (
-- Common signals
-- Common signals
clk_i : in std_logic;
reset_i : in std_logic;
transfer_done_o : out std_logic;
......@@ -91,7 +91,6 @@ architecture RTL of wb_dma is
signal sl_sel_we, m_sel_we, m_sel : std_logic_vector(c_sell -1 downto 0);
signal advance_m_adr, inc_m_adr : std_logic;
signal is_m_ack_index_top_m1 : std_logic;
signal s_adr_step : unsigned(7 downto 0);
begin
-------------------------------------------------------------------------------
process(clk_i)
......@@ -259,22 +258,12 @@ begin
end if;
end process;
-------------------------------------------------------------------------------
process()
begin
s_adr_step <= to_unsigned(1, s_adr_step'length);
if sl_sel_i = "11111111" then
s_adr_step <= to_unsigned(1, s_adr_step'length);
end process;
process(m_adr, sl_adr_i, latch_psize, inc_m_adr)
begin
if latch_psize = '1' then
nx_m_adr <= unsigned(sl_adr_i);
elsif inc_m_adr = '1' then
nx_m_adr <= m_adr + s_adr_step;
nx_m_adr <= m_adr + 1;
else
nx_m_adr <= m_adr;
end if;
......
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