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VME64x core
Commit c29a9a04 authored by dpedrett's avatar dpedrett
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Vme64x_core with Interrupter and without Stall signal in the WB side 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@138 665b4545-5c6b-4c24-801b-41150b02b44b
parent f753f85e
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Showing with 2184 additions and 514 deletions
hdl/boards/vfc/rtl/IRQ_generator.vhd
View file @ c29a9a04
...@@ -44,7 +44,6 @@ architecture Behavioral of IRQ_generator is ...@@ -44,7 +44,6 @@ architecture Behavioral of IRQ_generator is
signal s_en_int : std_logic; signal s_en_int : std_logic;
type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD); type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD);
signal currs, nexts : t_FSM; signal currs, nexts : t_FSM;
signal RST_n_oversampled : std_logic;
signal s_IRQ_o : std_logic; signal s_IRQ_o : std_logic;
signal s_count : unsigned(31 downto 0); signal s_count : unsigned(31 downto 0);
signal s_Rd_Int_Count_delayed : std_logic; signal s_Rd_Int_Count_delayed : std_logic;
...@@ -53,14 +52,10 @@ signal s_count_int : unsigned(31 downto 0); ...@@ -53,14 +52,10 @@ signal s_count_int : unsigned(31 downto 0);
signal s_count_req : unsigned(31 downto 0); signal s_count_req : unsigned(31 downto 0);
signal s_incr : std_logic; signal s_incr : std_logic;
signal s_gen_irq : std_logic; signal s_gen_irq : std_logic;
signal s_count0 : std_logic;
signal s_Freq : std_logic_vector(31 downto 0);
begin begin
-- RST oversampled...The reset input is asincronous so is better to sample it
RSTinputSample : entity work.DoubleSigInputSample
port map(
sig_i => reset,
sig_o => RST_n_oversampled,
clk_i => clk_i
);
RDinputSample : entity work.DoubleSigInputSample RDinputSample : entity work.DoubleSigInputSample
port map( port map(
sig_i => Read_Int_Count, sig_i => Read_Int_Count,
...@@ -75,14 +70,36 @@ IRQOutputSample : entity work.FlipFlopD ...@@ -75,14 +70,36 @@ IRQOutputSample : entity work.FlipFlopD
reset => '0', reset => '0',
enable => '1' enable => '1'
); );
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then s_Freq <= (others => '0');
elsif s_count0 = '1' then
s_Freq <= Freq;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if s_count = 0 then
s_count0 <= '1';
else
s_count0 <= '0';
end if;
end if;
end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if unsigned(Freq) = 0 then if reset = '0' then s_en_int <= '0';
s_en_int <= '0'; elsif unsigned(s_Freq) = 0 then
s_en_int <= '0';
else else
s_en_int <= '1'; s_en_int <= '1';
end if; end if;
end if; end if;
end process; end process;
...@@ -90,7 +107,7 @@ end process; ...@@ -90,7 +107,7 @@ end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if RST_n_oversampled = '0' then s_count <= (others => '0'); if reset = '0' or s_pulse = '1' then s_count <= (others => '0');
elsif s_en_int = '1' then elsif s_en_int = '1' then
s_count <= s_count + 1; s_count <= s_count + 1;
end if; end if;
...@@ -100,7 +117,7 @@ end process; ...@@ -100,7 +117,7 @@ end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if s_en_int = '1' and unsigned(Freq) = s_count then if s_en_int = '1' and unsigned(s_Freq) = s_count then
s_pulse <= '1'; s_pulse <= '1';
else else
s_pulse <= '0'; s_pulse <= '0';
...@@ -111,8 +128,8 @@ end process; ...@@ -111,8 +128,8 @@ end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if RST_n_oversampled = '0' then s_count_int <= (others => '0'); if reset = '0' then s_count_int <= (others => '0');
elsif s_en_int = '1' then elsif s_en_int = '1' and s_pulse = '1' then
s_count_int <= s_count_int + 1; s_count_int <= s_count_int + 1;
end if; end if;
end if; end if;
...@@ -121,7 +138,7 @@ end process; ...@@ -121,7 +138,7 @@ end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if RST_n_oversampled = '0' then s_count_req <= (others => '0'); if reset = '0' then s_count_req <= (others => '0');
elsif s_incr = '1' then elsif s_incr = '1' then
s_count_req <= s_count_req + 1; s_count_req <= s_count_req + 1;
end if; end if;
...@@ -142,7 +159,7 @@ end process; ...@@ -142,7 +159,7 @@ end process;
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if RST_n_oversampled = '0' then currs <= IDLE; if reset = '0' then currs <= IDLE;
else currs <= nexts; else currs <= nexts;
end if; end if;
end if; end if;
...@@ -168,7 +185,7 @@ begin ...@@ -168,7 +185,7 @@ begin
nexts <= WAIT_INT_ACK; nexts <= WAIT_INT_ACK;
when WAIT_INT_ACK => when WAIT_INT_ACK =>
if INT_ack = '1' then if INT_ack = '0' then
nexts <= WAIT_RD; nexts <= WAIT_RD;
else else
nexts <= WAIT_INT_ACK; nexts <= WAIT_INT_ACK;
......
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ c29a9a04
...@@ -163,6 +163,7 @@ COMPONENT VME64xCore_Top ...@@ -163,6 +163,7 @@ COMPONENT VME64xCore_Top
STB_o : OUT std_logic; STB_o : OUT std_logic;
-- Add by Davide for debug: -- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0); leds : out std_logic_vector(7 downto 0);
reset_o : out std_logic;
WE_o : OUT std_logic WE_o : OUT std_logic
); );
END COMPONENT; END COMPONENT;
...@@ -208,6 +209,8 @@ signal clk_in : std_logic; ...@@ -208,6 +209,8 @@ signal clk_in : std_logic;
signal s_locked : std_logic; signal s_locked : std_logic;
signal s_fb : std_logic; signal s_fb : std_logic;
signal s_INT_ack : std_logic; signal s_INT_ack : std_logic;
signal s_rst : std_logic;
begin begin
Inst_VME64xCore_Top: VME64xCore_Top PORT MAP( Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
...@@ -250,6 +253,7 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP( ...@@ -250,6 +253,7 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
STALL_i => WbStall_i, -- STALL_i => WbStall_i, --
IRQ_i => WbIrq_i, -- IRQ_i => WbIrq_i, --
INT_ack => s_INT_ack, INT_ack => s_INT_ack,
reset_o => s_rst,
-- Add by Davide for debug: -- Add by Davide for debug:
leds => leds leds => leds
); );
...@@ -265,7 +269,7 @@ Inst_xwb_dpram: xwb_dpram ...@@ -265,7 +269,7 @@ Inst_xwb_dpram: xwb_dpram
) )
port map( port map(
clk_sys_i => clk_in, clk_sys_i => clk_in,
rst_n_i => Rst, rst_n_i => s_rst,
INT_ack => s_INT_ack, INT_ack => s_INT_ack,
slave1_i.cyc => WbCyc_o, slave1_i.cyc => WbCyc_o,
slave1_i.stb => WbStb_o, slave1_i.stb => WbStb_o,
...@@ -284,7 +288,7 @@ Inst_xwb_dpram: xwb_dpram ...@@ -284,7 +288,7 @@ Inst_xwb_dpram: xwb_dpram
Rst <= VME_RST_n_i and Reset; Rst <= VME_RST_n_i and Reset;
-- PLL_BASE_inst : PLL_BASE -- PLL_BASE_inst : PLL_BASE
-- generic map ( -- generic map (
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED" -- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
......
hdl/boards/vfc/rtl/xwb_dpram.vhd
View file @ c29a9a04
...@@ -97,16 +97,19 @@ signal s_sel_IntCount : std_logic; ...@@ -97,16 +97,19 @@ signal s_sel_IntCount : std_logic;
signal s_Int_Count_o : std_logic_vector(31 downto 0); signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0); signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic; signal s_Read_IntCount : std_logic;
signal s_rst : std_logic;
begin begin
s_rst <= not(rst_n_i);
s_q_o1 <= s_INT_COUNT & s_FREQ; s_q_o1 <= s_INT_COUNT & s_FREQ;
s_en_Freq <= '1' when (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 and s_bwea = "00001111") else '0'; s_en_Freq <= '1' when (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 and s_bwea = "00001111") else '0';
s_Int_Count_o1 <= slave1_i.dat(63 downto 32) when (s_bwea = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0) else s_Int_Count_o; s_Int_Count_o1 <= slave1_i.dat(63 downto 32) when (s_bwea = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0) else s_Int_Count_o;
s_Read_IntCount <= '1' when (slave1_i.we = '0' and slave1_i.sel = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0 and slave1_out.ack = '1') else '0'; s_Read_IntCount <= '1' when (slave1_i.we = '0' and slave1_i.sel = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0 and slave1_out.ack = '1') else '0';
-- Reg INT_COUNT -- Reg INT_COUNT
INT_COUNT : entity work.Reg32bit INT_COUNT : entity work.Reg32bit
port map( port map(
reset => rst_n_i, reset => s_rst,
enable => '1', enable => '1',
di => s_Int_Count_o1, di => s_Int_Count_o1,
do => s_INT_COUNT, do => s_INT_COUNT,
...@@ -115,7 +118,7 @@ INT_COUNT : entity work.Reg32bit ...@@ -115,7 +118,7 @@ INT_COUNT : entity work.Reg32bit
-- Reg FREQ -- Reg FREQ
FREQ : entity work.Reg32bit FREQ : entity work.Reg32bit
port map( port map(
reset => rst_n_i, reset => s_rst,
enable => s_en_Freq, enable => s_en_Freq,
di => slave1_i.dat(31 downto 0), di => slave1_i.dat(31 downto 0),
do => s_FREQ, do => s_FREQ,
...@@ -124,7 +127,7 @@ FREQ : entity work.Reg32bit ...@@ -124,7 +127,7 @@ FREQ : entity work.Reg32bit
Inst_IRQ_generator: IRQ_generator PORT MAP( Inst_IRQ_generator: IRQ_generator PORT MAP(
clk_i => clk_sys_i, clk_i => clk_sys_i,
reset => rst_n_i, reset => s_rst,
Freq => s_FREQ, Freq => s_FREQ,
Int_Count_i => s_INT_COUNT, Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount, Read_Int_Count => s_Read_IntCount,
...@@ -186,7 +189,7 @@ Inst_IRQ_generator: IRQ_generator PORT MAP( ...@@ -186,7 +189,7 @@ Inst_IRQ_generator: IRQ_generator PORT MAP(
process(clk_sys_i) process(clk_sys_i)
begin begin
if(rising_edge(clk_sys_i)) then if(rising_edge(clk_sys_i)) then
if(rst_n_i = '0') then if(s_rst = '0') then
slave1_out.ack <= '0'; -- it was slave1_out.ack and slave1_in in all the process slave1_out.ack <= '0'; -- it was slave1_out.ack and slave1_in in all the process
-- slave2_out.ack <= '0'; -- slave2_out.ack <= '0';
else else
......
hdl/boards/vfc/sim/testbench/VME64x_Package.vhd
View file @ c29a9a04
...@@ -32,7 +32,9 @@ package VME64x is ...@@ -32,7 +32,9 @@ package VME64x is
Vme64xAsN : std_logic; Vme64xAsN : std_logic;
Vme64xDs1N : std_logic; Vme64xDs1N : std_logic;
Vme64xDs0N : std_logic; Vme64xDs0N : std_logic;
Vme64xLWORDN : std_logic; Vme64xLWORDN : std_logic;
Vme64xIACK : std_logic;
Vme64xIACKIN : std_logic;
Vme64xWRITEN : std_logic; Vme64xWRITEN : std_logic;
Vme64xAM : Vme64xAddressModType; Vme64xAM : Vme64xAddressModType;
Vme64xADDR : Vme64xAddressType; Vme64xADDR : Vme64xAddressType;
...@@ -49,8 +51,9 @@ package VME64x is ...@@ -49,8 +51,9 @@ package VME64x is
Vme64xRetryN : std_logic; Vme64xRetryN : std_logic;
Vme64xADDR : Vme64xAddressType; Vme64xADDR : Vme64xAddressType;
Vme64xDATA : Vme64xDataType; Vme64xDATA : Vme64xDataType;
Vme64xLWORDN : std_logic; Vme64xLWORDN : std_logic;
Vme64xIACKOUT : std_logic;
Vme64xIRQ : std_logic_vector(6 downto 0);
end record; end record;
...@@ -61,7 +64,7 @@ type t_Buffer_BLT is array (0 to 66) of std_logic_vector(31 downto 0); -- f ...@@ -61,7 +64,7 @@ type t_Buffer_BLT is array (0 to 66) of std_logic_vector(31 downto 0); -- f
type t_Buffer_MBLT is array (0 to 258) of std_logic_vector(63 downto 0); -- for MBLT transfer type t_Buffer_MBLT is array (0 to 258) of std_logic_vector(63 downto 0); -- for MBLT transfer
--The buffer has 258 positions, not 256; the last position is for test the error if i transfer more of 256 bytes. --The buffer has 258 positions, not 256; the last position is for test the error if i transfer more of 256 bytes.
type t_dataTransferType is (D08Byte0, D08Byte1, D08Byte2, D08Byte3, D16Byte01, D16Byte23, D32); type t_dataTransferType is (D08Byte0, D08Byte1, D08Byte2, D08Byte3, D16Byte01, D16Byte23, D32); -- for D64 use dataTransferType D32!
type t_AddressingType is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK, type t_AddressingType is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK,
A64, A64_BLT, A64_MBLT, A64_LCK, A32_2eVME, A64_2eVME, A32_2eSST, A64_2eSST, error); A64, A64_BLT, A64_MBLT, A64_LCK, A32_2eVME, A64_2eVME, A32_2eSST, A64_2eSST, error);
...@@ -84,7 +87,7 @@ constant ADER1_A64 : std_logic_vector(31 downto 0) := "000000000000000000000000" ...@@ -84,7 +87,7 @@ constant ADER1_A64 : std_logic_vector(31 downto 0) := "000000000000000000000000"
constant ADER1_A64_BLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_BLT &"00"; constant ADER1_A64_BLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_BLT &"00";
constant ADER1_A64_MBLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_MBLT &"00"; constant ADER1_A64_MBLT : std_logic_vector(31 downto 0) := "000000000000000000000000" & c_A64_MBLT &"00";
constant ADER1_A64_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000"; constant ADER1_A64_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "000000000000000000000000000";
constant ADER2_A32_2eVME : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"01" &"01"; constant ADER2_A32_2eVME : std_logic_vector(31 downto 0) := BA(7 downto 3) & "00000000000000000" & x"01" &"01";
constant ADER2_A64_2eVME : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"02" &"01"; constant ADER2_A64_2eVME : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"02" &"01";
constant ADER2_A32_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"11" &"01"; constant ADER2_A32_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"11" &"01";
constant ADER2_A64_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"12" &"01"; constant ADER2_A64_2eSST : std_logic_vector(31 downto 0) := "0000000000000000000000" & x"12" &"01";
...@@ -138,7 +141,9 @@ constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000 ...@@ -138,7 +141,9 @@ constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000
constant c_FUNC0_ADER_2 : std_logic_vector := x"7FF67"; constant c_FUNC0_ADER_2 : std_logic_vector := x"7FF67";
constant c_FUNC0_ADER_3 : std_logic_vector := x"7FF63"; constant c_FUNC0_ADER_3 : std_logic_vector := x"7FF63";
constant c_MBLT_Endian : std_logic_vector := x"7Fbf0"; constant c_MBLT_Endian : std_logic_vector := x"7Ff53";
constant c_IRQ_Vector : std_logic_vector := x"7FF5F";
constant c_IRQ_level : std_logic_vector := x"7FF5B";
-- CR constant -- CR constant
constant c_StartDefinedCR : std_logic_vector := x"00000"; constant c_StartDefinedCR : std_logic_vector := x"00000";
constant c_EndDefinedCR : std_logic_vector := x"00FFF"; constant c_EndDefinedCR : std_logic_vector := x"00FFF";
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ c29a9a04
This diff is collapsed.
hdl/boards/vfc/sim/testbench/wave.do
View file @ c29a9a04
...@@ -10,6 +10,8 @@ add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_AM_i ...@@ -10,6 +10,8 @@ add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_AM_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_DS_n_i add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_DS_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_GA_i add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_GA_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_BBSY_n_i add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_BBSY_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_IACK_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_IACKOUT_n_o
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_IACKIN_n_i add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_IACKIN_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_LWORD_n_b add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_LWORD_n_b
add wave -noupdate -expand -group VME_signals -radix hexadecimal /vme64x_tb/VME_ADDR_b add wave -noupdate -expand -group VME_signals -radix hexadecimal /vme64x_tb/VME_ADDR_b
...@@ -39,8 +41,8 @@ add wave -noupdate -group {Don't care} /vme64x_tb/WriteInProgress ...@@ -39,8 +41,8 @@ add wave -noupdate -group {Don't care} /vme64x_tb/WriteInProgress
add wave -noupdate -group {Don't care} /vme64x_tb/rst_n_i add wave -noupdate -group {Don't care} /vme64x_tb/rst_n_i
add wave -noupdate -group {Don't care} /vme64x_tb/localAddress add wave -noupdate -group {Don't care} /vme64x_tb/localAddress
add wave -noupdate -group {Don't care} /vme64x_tb/s_dataToSendOut add wave -noupdate -group {Don't care} /vme64x_tb/s_dataToSendOut
add wave -noupdate -expand -group WB_SLAVE_IN_OUT -childformat {{/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.adr -radix hexadecimal} {/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.dat -radix hexadecimal}} -expand -subitemconfig {/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.adr {-height 16 -radix hexadecimal} /vme64x_tb/uut/Inst_xwb_dpram/slave1_i.dat {-radix hexadecimal}} /vme64x_tb/uut/Inst_xwb_dpram/slave1_i add wave -noupdate -expand -group WB_SLAVE_IN_OUT -childformat {{/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.adr -radix hexadecimal} {/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.dat -radix hexadecimal}} -expand -subitemconfig {/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.adr {-height 16 -radix hexadecimal} /vme64x_tb/uut/Inst_xwb_dpram/slave1_i.dat {-height 16 -radix hexadecimal}} /vme64x_tb/uut/Inst_xwb_dpram/slave1_i
add wave -noupdate -expand -group WB_SLAVE_IN_OUT -childformat {{/vme64x_tb/uut/Inst_xwb_dpram/slave1_o.dat -radix hexadecimal}} -expand -subitemconfig {/vme64x_tb/uut/Inst_xwb_dpram/slave1_o.dat {-radix hexadecimal}} /vme64x_tb/uut/Inst_xwb_dpram/slave1_o add wave -noupdate -expand -group WB_SLAVE_IN_OUT -childformat {{/vme64x_tb/uut/Inst_xwb_dpram/slave1_o.dat -radix hexadecimal}} -expand -subitemconfig {/vme64x_tb/uut/Inst_xwb_dpram/slave1_o.dat {-height 16 -radix hexadecimal}} /vme64x_tb/uut/Inst_xwb_dpram/slave1_o
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_CSRarray add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_CSRarray
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/currs add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/currs
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_cyc_i add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_cyc_i
...@@ -69,12 +71,35 @@ add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_sel_o ...@@ -69,12 +71,35 @@ add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_sel_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_we_o add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_we_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_stall_i add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_stall_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/transfer_done_i add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/transfer_done_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/VMEtoWB add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_IACKIN_n_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/WBtoVME add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_AS_n_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/s_VMEWriteInFifo add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_DS_n_i
add wave -noupdate -radix unsigned /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/s_addr add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_LWORD_n_i
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_ADDR_123
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/INT_Level
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/INT_Vector
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/INT_Req
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_IRQ_n_o
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_IACKOUT_n_o
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_DTACK_n_o
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/VME_DATA_o
add wave -noupdate -expand -group IRQ_Controller /vme64x_tb/uut/Inst_VME64xCore_Top/Inst_IRQ_Controller/currs
add wave -noupdate -expand -group IRQ_Generator /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/Freq
add wave -noupdate -expand -group IRQ_Generator -radix decimal /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/Int_Count_i
add wave -noupdate -expand -group IRQ_Generator /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/Read_Int_Count
add wave -noupdate -expand -group IRQ_Generator /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/INT_ack
add wave -noupdate -expand -group IRQ_Generator /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/IRQ_o
add wave -noupdate -expand -group IRQ_Generator -radix decimal /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/Int_Count_o
add wave -noupdate -expand -group IRQ_Generator /vme64x_tb/uut/Inst_xwb_dpram/Inst_IRQ_generator/currs
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_cardSel
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_funcMatch
add wave -noupdate -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_phase1addr
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_XAMtype
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_addrWidth
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_AMmatch
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_FUNC_ADER
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {36265000 ps} 0} WaveRestoreCursors {{Cursor 1} {91591032 ps} 0}
configure wave -namecolwidth 184 configure wave -namecolwidth 184
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
...@@ -89,4 +114,4 @@ configure wave -griddelta 40 ...@@ -89,4 +114,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {36160167 ps} {36521200 ps} WaveRestoreZoom {89690733 ps} {95279436 ps}
hdl/vme64x-core/rtl/IRQ_Controller.vhd
View file @ c29a9a04
...@@ -36,6 +36,7 @@ entity IRQ_Controller is ...@@ -36,6 +36,7 @@ entity IRQ_Controller is
VME_IRQ_n_o : out STD_LOGIC_VECTOR (6 downto 0); VME_IRQ_n_o : out STD_LOGIC_VECTOR (6 downto 0);
VME_IACKOUT_n_o : out STD_LOGIC; VME_IACKOUT_n_o : out STD_LOGIC;
VME_DTACK_n_o : out STD_LOGIC; VME_DTACK_n_o : out STD_LOGIC;
VME_DTACK_OE_o : out STD_LOGIC;
VME_DATA_o : out STD_LOGIC_VECTOR (31 downto 0); VME_DATA_o : out STD_LOGIC_VECTOR (31 downto 0);
DataDir : out STD_LOGIC); DataDir : out STD_LOGIC);
end IRQ_Controller; end IRQ_Controller;
...@@ -52,6 +53,7 @@ signal INT_Req_sample : std_logic; ...@@ -52,6 +53,7 @@ signal INT_Req_sample : std_logic;
--signal Read_Int_Source_sample : std_logic; --signal Read_Int_Source_sample : std_logic;
--output signals --output signals
signal s_DTACK : std_logic; signal s_DTACK : std_logic;
signal s_DTACK_OE : std_logic;
signal s_DataDir : std_logic; signal s_DataDir : std_logic;
signal s_IACKOUT : std_logic; signal s_IACKOUT : std_logic;
signal s_IRQ : std_logic_vector(6 downto 0); signal s_IRQ : std_logic_vector(6 downto 0);
...@@ -261,7 +263,7 @@ begin ...@@ -261,7 +263,7 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '1'; s_resetIRQ <= '1';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '0';
when IRQ => when IRQ =>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
s_DataDir <= '0'; s_DataDir <= '0';
...@@ -269,7 +271,8 @@ begin ...@@ -269,7 +271,8 @@ begin
s_enableIRQ <= '1'; s_enableIRQ <= '1';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '0';
when WAIT_AS => when WAIT_AS =>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
s_DataDir <= '0'; s_DataDir <= '0';
...@@ -277,6 +280,7 @@ begin ...@@ -277,6 +280,7 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '0';
when WAIT_DS => when WAIT_DS =>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
...@@ -285,6 +289,7 @@ begin ...@@ -285,6 +289,7 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '0';
when LATCH_DS => when LATCH_DS =>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
...@@ -293,6 +298,7 @@ begin ...@@ -293,6 +298,7 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '1'; DSlatch <= '1';
s_DTACK_OE <= '0';
when ACK_INT => when ACK_INT =>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
...@@ -301,6 +307,7 @@ begin ...@@ -301,6 +307,7 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '0';
when IACKOUT => when IACKOUT =>
s_IACKOUT <= '0'; s_IACKOUT <= '0';
...@@ -309,7 +316,8 @@ begin ...@@ -309,7 +316,8 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '0';
when DATA_OUT=> when DATA_OUT=>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
s_DataDir <= '1'; s_DataDir <= '1';
...@@ -317,14 +325,16 @@ begin ...@@ -317,14 +325,16 @@ begin
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '0'; s_resetIRQ <= '0';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '1';
when DTACK=> when DTACK=>
s_IACKOUT <= '1'; s_IACKOUT <= '1';
s_DataDir <= '1'; s_DataDir <= '1';
s_DTACK <= '0'; s_DTACK <= '0';
s_enableIRQ <= '0'; s_enableIRQ <= '0';
s_resetIRQ <= '1'; s_resetIRQ <= '1';
DSlatch <= '0'; DSlatch <= '0';
s_DTACK_OE <= '1';
end case; end case;
...@@ -379,7 +389,8 @@ begin ...@@ -379,7 +389,8 @@ begin
end if; end if;
end if; end if;
end process; end process;
s_ack_int <= (not(VME_DS_latched(0))) and (not(VME_DS_latched(1))) and (not(VME_LWORD_latched)) and ADDRmatch; s_ack_int <= (not(VME_DS_latched(0))) and ADDRmatch; --and (not(VME_LWORD_latched)) and (not(VME_DS_latched(1)))
s_Data <= x"000000" & INT_Vector; s_Data <= x"000000" & INT_Vector;
VME_DTACK_OE_o <= s_DTACK_OE;
end Behavioral; end Behavioral;
hdl/vme64x-core/rtl/SharedComps.vhd
View file @ c29a9a04
...@@ -84,17 +84,20 @@ entity Reg32bit is ...@@ -84,17 +84,20 @@ entity Reg32bit is
); );
end Reg32bit; end Reg32bit;
architecture RTL of Reg32bit is architecture RTL of Reg32bit is
signal s_reg : std_logic_vector(31 downto 0); --signal s_reg : std_logic_vector(31 downto 0);
begin begin
process(clk_i) process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if reset = '0' then s_reg <= (others => '0'); if reset = '0' then
do <= (others => '0');
--s_reg <= (others => '0');
elsif enable = '1' then elsif enable = '1' then
s_reg <= di; do <= di;
--s_reg <= di;
end if; end if;
do <= s_reg; end if;
end if; --do <= s_reg;
end process; end process;
end RTL; end RTL;
......
hdl/vme64x-core/rtl/VME64xCore_NoIpTop.vhd
View file @ c29a9a04
...@@ -97,8 +97,8 @@ entity VME64xCore_Top is ...@@ -97,8 +97,8 @@ entity VME64xCore_Top is
INT_ack : out std_logic; INT_ack : out std_logic;
IRQ_i : in std_logic; IRQ_i : in std_logic;
-- Add by Davide for debug: -- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0) leds : out std_logic_vector(7 downto 0);
reset_o : out std_logic
-- Uncomment this for use of external CR and CRAM -- Uncomment this for use of external CR and CRAM
-- -- CROM -- -- CROM
-- CRaddr_o: out std_logic_vector(18 downto 0); -- CRaddr_o: out std_logic_vector(18 downto 0);
...@@ -225,6 +225,7 @@ architecture RTL of VME64xCore_Top is ...@@ -225,6 +225,7 @@ architecture RTL of VME64xCore_Top is
VME_IRQ_n_o : OUT std_logic_vector(6 downto 0); VME_IRQ_n_o : OUT std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : OUT std_logic; VME_IACKOUT_n_o : OUT std_logic;
VME_DTACK_n_o : OUT std_logic; VME_DTACK_n_o : OUT std_logic;
VME_DTACK_OE_o : OUT std_logic;
VME_DATA_o : OUT std_logic_vector(31 downto 0); VME_DATA_o : OUT std_logic_vector(31 downto 0);
DataDir : OUT std_logic DataDir : OUT std_logic
); );
...@@ -305,11 +306,14 @@ architecture RTL of VME64xCore_Top is ...@@ -305,11 +306,14 @@ architecture RTL of VME64xCore_Top is
signal s_fifo : std_logic; signal s_fifo : std_logic;
signal VME_DTACK_VMEbus : std_logic; signal VME_DTACK_VMEbus : std_logic;
signal VME_DTACK_IRQ : std_logic; signal VME_DTACK_IRQ : std_logic;
signal VME_DTACK_OE_VMEbus : std_logic;
signal VME_DTACK_OE_IRQ : std_logic;
signal s_VME_DATA_DIR_VMEbus : std_logic; signal s_VME_DATA_DIR_VMEbus : std_logic;
signal s_VME_DATA_DIR_IRQ : std_logic; signal s_VME_DATA_DIR_IRQ : std_logic;
signal s_INT_Level : std_logic_vector(7 downto 0); signal s_INT_Level : std_logic_vector(7 downto 0);
signal s_INT_Vector : std_logic_vector(7 downto 0); signal s_INT_Vector : std_logic_vector(7 downto 0);
signal s_VME_IRQ_n_o : std_logic_vector(6 downto 0); signal s_VME_IRQ_n_o : std_logic_vector(6 downto 0);
signal s_reset_IRQ : std_logic;
--signal s_Read_Int_Source : std_logic; --signal s_Read_Int_Source : std_logic;
begin begin
...@@ -352,7 +356,7 @@ architecture RTL of VME64xCore_Top is ...@@ -352,7 +356,7 @@ architecture RTL of VME64xCore_Top is
VME_BBSY_n_i => VME_BBSY_n_i, VME_BBSY_n_i => VME_BBSY_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i, VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i, VME_IACK_n_i => VME_IACK_n_i,
VME_DTACK_OE_o => VME_DTACK_OE_o, VME_DTACK_OE_o => VME_DTACK_OE_VMEbus,
clk_i => clk_i, clk_i => clk_i,
reset_o => s_reset, reset_o => s_reset,
...@@ -494,7 +498,9 @@ wbtovme <= '0' when s_fifo = '0' else s_wbtovme; ...@@ -494,7 +498,9 @@ wbtovme <= '0' when s_fifo = '0' else s_wbtovme;
s_VME_DATA_b_o <= s_VME_DATA_VMEbus WHEN VME_IACK_n_i ='1' ELSE s_VME_DATA_b_o <= s_VME_DATA_VMEbus WHEN VME_IACK_n_i ='1' ELSE
s_VME_DATA_IRQ; s_VME_DATA_IRQ;
VME_DTACK_n_o <= VME_DTACK_VMEbus WHEN VME_IACK_n_i ='1' ELSE VME_DTACK_n_o <= VME_DTACK_VMEbus WHEN VME_IACK_n_i ='1' ELSE
VME_DTACK_IRQ; VME_DTACK_IRQ;
VME_DTACK_OE_o <= VME_DTACK_OE_VMEbus WHEN VME_IACK_n_i ='1' ELSE
VME_DTACK_OE_IRQ;
s_VME_DATA_DIR <= s_VME_DATA_DIR_VMEbus WHEN VME_IACK_n_i ='1' ELSE s_VME_DATA_DIR <= s_VME_DATA_DIR_VMEbus WHEN VME_IACK_n_i ='1' ELSE
s_VME_DATA_DIR_IRQ; s_VME_DATA_DIR_IRQ;
...@@ -502,7 +508,7 @@ s_VME_DATA_DIR <= s_VME_DATA_DIR_VMEbus WHEN VME_IACK_n_i ='1' ELSE ...@@ -502,7 +508,7 @@ s_VME_DATA_DIR <= s_VME_DATA_DIR_VMEbus WHEN VME_IACK_n_i ='1' ELSE
Inst_IRQ_Controller: IRQ_Controller PORT MAP( Inst_IRQ_Controller: IRQ_Controller PORT MAP(
clk_i => clk_i, clk_i => clk_i,
reset => VME_RST_n_i, reset => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_i, VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_AS_n_i => VME_AS_n_i, VME_AS_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_i, VME_DS_n_i => VME_DS_n_i,
...@@ -515,6 +521,7 @@ Inst_IRQ_Controller: IRQ_Controller PORT MAP( ...@@ -515,6 +521,7 @@ Inst_IRQ_Controller: IRQ_Controller PORT MAP(
VME_IRQ_n_o => s_VME_IRQ_n_o, VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o, VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_n_o => VME_DTACK_IRQ, VME_DTACK_n_o => VME_DTACK_IRQ,
VME_DTACK_OE_o => VME_DTACK_OE_IRQ,
VME_DATA_o => s_VME_DATA_IRQ, VME_DATA_o => s_VME_DATA_IRQ,
DataDir => s_VME_DATA_DIR_IRQ DataDir => s_VME_DATA_DIR_IRQ
); );
...@@ -524,6 +531,8 @@ s_irqDTACK <= '0'; ...@@ -524,6 +531,8 @@ s_irqDTACK <= '0';
s_IACKinProgress <= '0'; s_IACKinProgress <= '0';
s_IDtoData <= '0'; s_IDtoData <= '0';
INT_ack <= VME_DTACK_IRQ; INT_ack <= VME_DTACK_IRQ;
reset_o <= s_reset;
s_reset_IRQ <= not(s_reset);
--s_IRQlevelReg <= (others => '0'); --s_IRQlevelReg <= (others => '0');
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
process(clk_i) process(clk_i)
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ c29a9a04
This diff is collapsed.
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ c29a9a04
...@@ -14,42 +14,44 @@ BIT_SET_CLR_REG => x"10", --Bit set register -- 0x10=module enable ...@@ -14,42 +14,44 @@ BIT_SET_CLR_REG => x"10", --Bit set register -- 0x10=module enable
USR_BIT_SET_CLR_REG => x"00", --Bit clear register USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER CRAM_OWNER => x"00", --CRAM_OWNER
FUNC0_ADER_0 =>x"08", -- it was x"45" FUNC0_ADER_0 =>x"09", -- it was x"45"
FUNC0_ADER_1 =>x"00", FUNC0_ADER_1 =>x"00",
FUNC0_ADER_2 =>x"00", FUNC0_ADER_2 =>x"00",
FUNC0_ADER_3 =>x"c0", -- it was x"80" FUNC0_ADER_3 =>x"c0", -- it was x"80"
FUNC1_ADER_0 =>x"00", FUNC1_ADER_0 =>x"39",
FUNC1_ADER_1 =>x"00", FUNC1_ADER_1 =>x"00",
FUNC1_ADER_2 =>x"00", -- it was x"34" FUNC1_ADER_2 =>x"c0", -- it was x"34"
FUNC1_ADER_3 =>x"00", -- it was x"12" FUNC1_ADER_3 =>x"00", -- it was x"12"
FUNC2_ADER_0 =>x"00", -- it was x"e4" FUNC2_ADER_0 =>x"08", -- it was x"e4"
FUNC2_ADER_1 =>x"00", FUNC2_ADER_1 =>x"00",
FUNC2_ADER_2 =>x"00", -- it was x"80" FUNC2_ADER_2 =>x"00", -- it was x"80"
FUNC2_ADER_3 =>x"00", FUNC2_ADER_3 =>x"c0",
FUNC3_ADER_0 =>x"24", FUNC3_ADER_0 =>x"04", -- A64_S
FUNC3_ADER_1 =>x"00", FUNC3_ADER_1 =>x"00",
FUNC3_ADER_2 =>x"00", FUNC3_ADER_2 =>x"00",
FUNC3_ADER_3 =>x"80", FUNC3_ADER_3 =>x"00",
FUNC4_ADER_0 =>x"44", FUNC4_ADER_0 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_1 =>x"00", FUNC4_ADER_1 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_2 =>x"00", FUNC4_ADER_2 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_3 =>x"00", FUNC4_ADER_3 =>x"c0", --used for decoding the FUNC3
FUNC5_ADER_0 =>x"00", FUNC5_ADER_0 =>x"01",
FUNC5_ADER_1 =>x"00", FUNC5_ADER_1 =>x"00",
FUNC5_ADER_2 =>x"34", FUNC5_ADER_2 =>x"00",
FUNC5_ADER_3 =>x"11", FUNC5_ADER_3 =>x"c0",
FUNC6_ADER_0 =>x"00", FUNC6_ADER_0 =>x"00",
FUNC6_ADER_1 =>x"00", FUNC6_ADER_1 =>x"00",
FUNC6_ADER_2 =>x"00", FUNC6_ADER_2 =>x"00",
FUNC6_ADER_3 =>x"80", FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"86",
IRQ_level =>x"02",
others => (others => '0')); others => (others => '0'));
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ c29a9a04
This diff is collapsed.
hdl/vme64x-core/rtl/VME_pack.vhd
View file @ c29a9a04
...@@ -40,8 +40,10 @@ package VME_pack is ...@@ -40,8 +40,10 @@ package VME_pack is
constant c_A64_MBLT : std_logic_vector(5 downto 0) := "000000"; constant c_A64_MBLT : std_logic_vector(5 downto 0) := "000000";
constant c_A64_LCK : std_logic_vector(5 downto 0) := "000100"; constant c_A64_LCK : std_logic_vector(5 downto 0) := "000100";
constant c_TWOedge : std_logic_vector(5 downto 0) := "100000"; constant c_TWOedge : std_logic_vector(5 downto 0) := "100000";
constant c_A32_2eVME : std_logic_vector(7 downto 0) := "00000001";
constant c_A64_2eVME : std_logic_vector(7 downto 0) := "00000010";
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001";
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010";
constant c_cr_step : integer := 4; constant c_cr_step : integer := 4;
constant BAR : integer := 255; constant BAR : integer := 255;
......
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