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VME64x core
Commit f753f85e authored by dpedrett's avatar dpedrett
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vme64x with Interrupter 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@137 665b4545-5c6b-4c24-801b-41150b02b44b
parent 0a97c63b
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Showing with 1172 additions and 247 deletions
hdl/boards/vfc/SFpga.ucf
View file @ f753f85e
......@@ -41,7 +41,7 @@ NET "VME_DATA_b[29]" LOC = Y16;
NET "VME_DATA_b[30]" LOC = Y15;
NET "VME_DATA_b[31]" LOC = W14;
#NET "VME_IACK_i" LOC = F18; not used becouse my core is in the slot 8
NET "VME_IACK_n_i" LOC = F18;
NET "VME_RETRY_OE_o" LOC = F17;
NET "VME_RETRY_n_o" LOC = G17;
NET "VME_RST_n_i" LOC = J16;
......
hdl/boards/vfc/rtl/IRQ_generator.vhd 0 → 100644
View file @ f753f85e
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:18:01 06/13/2012
-- Design Name:
-- Module Name: IRQ_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IRQ_generator is
Port ( clk_i : in STD_LOGIC;
reset : in STD_LOGIC;
Freq : in STD_LOGIC_VECTOR (31 downto 0);
Int_Count_i : in STD_LOGIC_VECTOR (31 downto 0);
Read_Int_Count : in STD_LOGIC;
INT_ack : in STD_LOGIC;
IRQ_o : out STD_LOGIC;
Int_Count_o : out STD_LOGIC_VECTOR (31 downto 0));
end IRQ_generator;
architecture Behavioral of IRQ_generator is
signal s_en_int : std_logic;
type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD);
signal currs, nexts : t_FSM;
signal RST_n_oversampled : std_logic;
signal s_IRQ_o : std_logic;
signal s_count : unsigned(31 downto 0);
signal s_Rd_Int_Count_delayed : std_logic;
signal s_pulse : std_logic;
signal s_count_int : unsigned(31 downto 0);
signal s_count_req : unsigned(31 downto 0);
signal s_incr : std_logic;
signal s_gen_irq : std_logic;
begin
-- RST oversampled...The reset input is asincronous so is better to sample it
RSTinputSample : entity work.DoubleSigInputSample
port map(
sig_i => reset,
sig_o => RST_n_oversampled,
clk_i => clk_i
);
RDinputSample : entity work.DoubleSigInputSample
port map(
sig_i => Read_Int_Count,
sig_o => s_Rd_Int_Count_delayed,
clk_i => clk_i
);
IRQOutputSample : entity work.FlipFlopD
port map(
sig_i => s_IRQ_o,
sig_o => IRQ_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
process(clk_i)
begin
if rising_edge(clk_i) then
if unsigned(Freq) = 0 then
s_en_int <= '0';
else
s_en_int <= '1';
end if;
end if;
end process;
--Counter
process(clk_i)
begin
if rising_edge(clk_i) then
if RST_n_oversampled = '0' then s_count <= (others => '0');
elsif s_en_int = '1' then
s_count <= s_count + 1;
end if;
end if;
end process;
--
process(clk_i)
begin
if rising_edge(clk_i) then
if s_en_int = '1' and unsigned(Freq) = s_count then
s_pulse <= '1';
else
s_pulse <= '0';
end if;
end if;
end process;
--Counter interrupts
process(clk_i)
begin
if rising_edge(clk_i) then
if RST_n_oversampled = '0' then s_count_int <= (others => '0');
elsif s_en_int = '1' then
s_count_int <= s_count_int + 1;
end if;
end if;
end process;
--Counter interrupts requests
process(clk_i)
begin
if rising_edge(clk_i) then
if RST_n_oversampled = '0' then s_count_req <= (others => '0');
elsif s_incr = '1' then
s_count_req <= s_count_req + 1;
end if;
end if;
end process;
--
process(clk_i)
begin
if rising_edge(clk_i) then
if unsigned(Int_Count_i) > s_count_req then
s_gen_irq <= '1';
else
s_gen_irq <= '0';
end if;
end if;
end process;
-- Update current state
process(clk_i)
begin
if rising_edge(clk_i) then
if RST_n_oversampled = '0' then currs <= IDLE;
else currs <= nexts;
end if;
end if;
end process;
process(currs,s_gen_irq,INT_ack,s_Rd_Int_Count_delayed)
begin
case currs is
when IDLE =>
nexts <= CHECK;
when CHECK =>
if s_gen_irq = '1' then
nexts <= INCR;
else
nexts <= CHECK;
end if;
when INCR =>
nexts <= IRQ;
when IRQ =>
nexts <= WAIT_INT_ACK;
when WAIT_INT_ACK =>
if INT_ack = '1' then
nexts <= WAIT_RD;
else
nexts <= WAIT_INT_ACK;
end if;
when WAIT_RD =>
if s_Rd_Int_Count_delayed = '1' then
nexts <= IDLE;
else
nexts <= WAIT_RD;
end if;
end case;
end process;
process(currs)
begin
case currs is
when IDLE =>
s_incr <= '0';
s_IRQ_o <= '0';
when CHECK =>
s_incr <= '0';
s_IRQ_o <= '0';
when INCR =>
s_incr <= '1';
s_IRQ_o <= '0';
when IRQ =>
s_incr <= '0';
s_IRQ_o <= '1';
when WAIT_INT_ACK =>
s_incr <= '0';
s_IRQ_o <= '0';
when WAIT_RD =>
s_incr <= '0';
s_IRQ_o <= '0';
end case;
end process;
Int_Count_o <= std_logic_vector(s_count_int);
end Behavioral;
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ f753f85e
......@@ -68,13 +68,15 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
--Library UNISIM;
--use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
......@@ -100,7 +102,7 @@ port(
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACK_n_i : in std_logic; --Added by Davide
-- VME buffers
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
......@@ -130,13 +132,15 @@ COMPONENT VME64xCore_Top
VME_GA_i : IN std_logic_vector(5 downto 0);
VME_BBSY_n_i : IN std_logic;
VME_IACKIN_n_i : IN std_logic;
VME_IACK_n_i : in std_logic;
RST_i : IN std_logic;
DAT_i : IN std_logic_vector(63 downto 0);
ERR_i : IN std_logic;
RTY_i : IN std_logic;
ACK_i : IN std_logic;
STALL_i : IN std_logic;
IRQ_i : IN std_logic;
IRQ_i : IN std_logic;
INT_ack : OUT std_logic;
VME_LWORD_n_b : INOUT std_logic;
VME_ADDR_b : INOUT std_logic_vector(31 downto 1);
VME_DATA_b : INOUT std_logic_vector(31 downto 0);
......@@ -174,6 +178,7 @@ COMPONENT xwb_dpram
PORT(
clk_sys_i : IN std_logic;
rst_n_i : IN std_logic;
INT_ack : IN std_logic;
slave1_i : IN t_wishbone_slave_in;
slave1_o : OUT t_wishbone_slave_out
);
......@@ -193,17 +198,20 @@ signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
signal clk_40MHz : std_logic;
--signal clk_40MHz : std_logic;
signal clk_fb : std_logic;
--signal clk_2 : std_logic;
--signal status : std_logic_vector(1 downto 0);
signal locked : std_logic;
--signal clk_180 : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
begin
Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
clk_i => clk_i,
clk_i => clk_in,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => Rst,
VME_WRITE_n_i => VME_WRITE_n_i,
......@@ -220,6 +228,7 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
......@@ -240,6 +249,7 @@ Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
WE_o => WbWe_o, --
STALL_i => WbStall_i, --
IRQ_i => WbIrq_i, --
INT_ack => s_INT_ack,
-- Add by Davide for debug:
leds => leds
);
......@@ -254,8 +264,9 @@ Inst_xwb_dpram: xwb_dpram
g_slave1_granularity => BYTE
)
port map(
clk_sys_i => clk_i,
rst_n_i => Reset,
clk_sys_i => clk_in,
rst_n_i => Rst,
INT_ack => s_INT_ack,
slave1_i.cyc => WbCyc_o,
slave1_i.stb => WbStb_o,
slave1_i.adr => WbAdr_o,
......@@ -274,7 +285,55 @@ Inst_xwb_dpram: xwb_dpram
Rst <= VME_RST_n_i and Reset;
-- PLL_BASE_inst : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
-- CLKFBOUT_MULT => 30, -- Multiply value for all CLKOUT clock outputs (1-64)
-- CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- -- (0.0-360.0).
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-- CLKOUT0_DIVIDE => 30,
-- CLKOUT1_DIVIDE => 1,
-- CLKOUT2_DIVIDE => 1,
-- CLKOUT3_DIVIDE => 1,
-- CLKOUT4_DIVIDE => 1,
-- CLKOUT5_DIVIDE => 1,
-- -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKOUT3_DUTY_CYCLE => 0.500,
-- CLKOUT4_DUTY_CYCLE => 0.500,
-- CLKOUT5_DUTY_CYCLE => 0.500,
-- -- CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT3_PHASE => 0.000,
-- CLKOUT4_PHASE => 0.000,
-- CLKOUT5_PHASE => 0.000,
-- CLK_FEEDBACK => "CLKFBOUT", -- Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
-- COMPENSATION => "SYSTEM_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
-- DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
-- REF_JITTER => 0.1, -- Reference Clock Jitter in UI (0.000-0.999).
-- RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
-- )
-- port map (
-- CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
-- CLKOUT0 => clk_in, --clk 50 MHz
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
-- CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
-- CLKIN => clk_i, -- 1-bit input: Clock input
-- RST => '0' -- 1-bit input: Reset input
-- );
clk_in <= clk_i;
end Behavioral;
hdl/boards/vfc/rtl/xwb_dpram.vhd
View file @ f753f85e
......@@ -45,6 +45,7 @@ entity xwb_dpram is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
INT_ack : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
--slave2_i : in t_wishbone_slave_in;
......@@ -70,43 +71,69 @@ architecture struct of xwb_dpram is
signal slave1_out : t_wishbone_slave_out;
--signal slave2_in : t_wishbone_slave_in;
--signal slave2_out : t_wishbone_slave_out;
signal s_cyc : std_logic;
signal s_stb : std_logic;
COMPONENT IRQ_generator
PORT(
clk_i : IN std_logic;
reset : IN std_logic;
Freq : IN std_logic_vector(31 downto 0);
Int_Count_i : IN std_logic_vector(31 downto 0);
Read_Int_Count : IN std_logic;
INT_ack : IN std_logic;
IRQ_o : OUT std_logic;
Int_Count_o : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal s_INT_COUNT : std_logic_vector(31 downto 0);
signal s_FREQ : std_logic_vector(31 downto 0);
signal s_q_o : std_logic_vector(63 downto 0);
signal s_q_o1 : std_logic_vector(63 downto 0);
signal s_en_Freq : std_logic;
signal s_sel_IntCount : std_logic;
--signal s_IRQ : std_logic;
signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Int_Count_o1 : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
begin
-- U_Adapter1 : wb_slave_adapter
-- generic map (
-- g_master_use_struct => true,
-- g_master_mode => g_slave1_interface_mode,
-- g_master_granularity => BYTE,
-- g_slave_use_struct => true,
-- g_slave_mode => g_slave1_interface_mode,
-- g_slave_granularity => g_slave1_granularity)
-- port map (
-- clk_sys_i => clk_sys_i,
-- rst_n_i => rst_n_i,
-- slave_i => slave1_i,
-- slave_o => slave1_o);
-- master_i => slave1_out,
-- master_o => slave1_in);
s_q_o1 <= s_INT_COUNT & s_FREQ;
s_en_Freq <= '1' when (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 and s_bwea = "00001111") else '0';
s_Int_Count_o1 <= slave1_i.dat(63 downto 32) when (s_bwea = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0) else s_Int_Count_o;
s_Read_IntCount <= '1' when (slave1_i.we = '0' and slave1_i.sel = "11110000" and (unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0))) = 0 and slave1_out.ack = '1') else '0';
-- Reg INT_COUNT
INT_COUNT : entity work.Reg32bit
port map(
reset => rst_n_i,
enable => '1',
di => s_Int_Count_o1,
do => s_INT_COUNT,
clk_i => clk_sys_i
);
-- Reg FREQ
FREQ : entity work.Reg32bit
port map(
reset => rst_n_i,
enable => s_en_Freq,
di => slave1_i.dat(31 downto 0),
do => s_FREQ,
clk_i => clk_sys_i
);
Inst_IRQ_generator: IRQ_generator PORT MAP(
clk_i => clk_sys_i,
reset => rst_n_i,
Freq => s_FREQ,
Int_Count_i => s_INT_COUNT,
Read_Int_Count => s_Read_IntCount,
INT_ack => INT_ack,
IRQ_o => slave1_o.int,
Int_Count_o => s_Int_Count_o
);
--U_Adapter2 : wb_slave_adapter
-- generic map (
-- g_master_use_struct => true,
-- g_master_mode => g_slave2_interface_mode,
-- g_master_granularity => BYTE,
-- g_slave_use_struct => true,
-- g_slave_mode => g_slave2_interface_mode,
-- g_slave_granularity => g_slave2_granularity)
-- port map (
-- clk_sys_i => clk_sys_i,
-- rst_n_i => rst_n_i,
-- slave_i => slave2_i,
-- slave_o => slave2_o,
-- master_i => slave2_out,
-- master_o => slave2_in);
U_DPRAM : entity work.spram
generic map(
......@@ -125,7 +152,7 @@ begin
-- we_i => s_wea,
a_i => slave1_i.adr(f_log2_size(g_size)-1 downto 0), -- it was slave1_in.adr
d_i => slave1_i.dat, -- it was slave1_in.adr
q_o => slave1_o.dat -- it was slave1_out.dat
q_o => s_q_o -- it was slave1_out.dat
);
......@@ -153,7 +180,7 @@ begin
s_bwea <= slave1_i.sel when s_wea = '1' else f_zeros(c_wishbone_data_width/8); --it was slave1_in.sel
-- s_bweb <= slave2_in.sel when s_web = '1' else f_zeros(c_wishbone_data_width/8);
s_wea <= slave1_i.we and slave1_i.stb and slave1_i.cyc; -- it was slave1_in.we and slave1_in.stb and slave1_in.cyc;
s_wea <= slave1_i.we and slave1_i.cyc and slave1_i.stb; -- it was slave1_in.we and slave1_in.stb and slave1_in.cyc;
--s_web <= slave2_in.we and slave2_in.stb and slave2_in.cyc;
process(clk_sys_i)
......@@ -178,6 +205,7 @@ begin
end if;
end process;
slave1_o.dat <= s_q_o1 when unsigned(slave1_i.adr(f_log2_size(g_size)-1 downto 0)) = 0 else s_q_o;
slave1_o.stall <= '0';
-- slave2_out.stall <= '0';
slave1_o.err <= '0';
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ f753f85e
This diff is collapsed.
hdl/boards/vfc/sim/testbench/wave.do 0 → 100644
View file @ f753f85e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /vme64x_tb/clk_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_mainFSMstate
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_AS_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_RST_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_WRITE_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_typeOfDataTransfer
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_AM_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_DS_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_GA_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_BBSY_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_IACKIN_n_i
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_LWORD_n_b
add wave -noupdate -expand -group VME_signals -radix hexadecimal /vme64x_tb/VME_ADDR_b
add wave -noupdate -expand -group VME_signals -radix hexadecimal /vme64x_tb/VME_DATA_b
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_BERR_o
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_DTACK_n_o
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_RETRY_n_o
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_DATA_DIR_o
add wave -noupdate -expand -group VME_signals /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_sel
add wave -noupdate -expand -group VME_signals /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_beatCount
add wave -noupdate -expand -group VME_signals /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_addrOffset
add wave -noupdate -expand -group VME_signals /vme64x_tb/VME_ADDR_DIR_o
add wave -noupdate /vme64x_tb/RST_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_BERRcondition
add wave -noupdate /vme64x_tb/s_dataTransferType
add wave -noupdate /vme64x_tb/s_AddressingType
add wave -noupdate /vme64x_tb/s_dataToSend
add wave -noupdate -radix hexadecimal /vme64x_tb/s_dataToReceive
add wave -noupdate /vme64x_tb/s_address
add wave -noupdate -group VME_MASTER_IN_OUT /vme64x_tb/VME64xBus_out
add wave -noupdate -group VME_MASTER_IN_OUT /vme64x_tb/VME64xBus_in
add wave -noupdate -group {Don't care} /vme64x_tb/VME_IRQ_n_o
add wave -noupdate -group {Don't care} /vme64x_tb/VME_IACKOUT_n_o
add wave -noupdate -group {Don't care} /vme64x_tb/VME_DTACK_OE_o
add wave -noupdate -group {Don't care} /vme64x_tb/ReadInProgress
add wave -noupdate -group {Don't care} /vme64x_tb/WriteInProgress
add wave -noupdate -group {Don't care} /vme64x_tb/rst_n_i
add wave -noupdate -group {Don't care} /vme64x_tb/localAddress
add wave -noupdate -group {Don't care} /vme64x_tb/s_dataToSendOut
add wave -noupdate -expand -group WB_SLAVE_IN_OUT -childformat {{/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.adr -radix hexadecimal} {/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.dat -radix hexadecimal}} -expand -subitemconfig {/vme64x_tb/uut/Inst_xwb_dpram/slave1_i.adr {-height 16 -radix hexadecimal} /vme64x_tb/uut/Inst_xwb_dpram/slave1_i.dat {-radix hexadecimal}} /vme64x_tb/uut/Inst_xwb_dpram/slave1_i
add wave -noupdate -expand -group WB_SLAVE_IN_OUT -childformat {{/vme64x_tb/uut/Inst_xwb_dpram/slave1_o.dat -radix hexadecimal}} -expand -subitemconfig {/vme64x_tb/uut/Inst_xwb_dpram/slave1_o.dat {-radix hexadecimal}} /vme64x_tb/uut/Inst_xwb_dpram/slave1_o
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/VME_bus_1/s_CSRarray
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/currs
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_cyc_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_stb_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_ack_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_err_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_lock_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_rty_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_sel_i
add wave -noupdate -group FIFO -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_adr_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_we_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_stall_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_psize_i
add wave -noupdate -group FIFO -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_dat_o
add wave -noupdate -group FIFO -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/sl_dat_i
add wave -noupdate -group FIFO -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_dat_i
add wave -noupdate -group FIFO -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_dat_o
add wave -noupdate -group FIFO -radix hexadecimal /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_adr_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_cyc_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_stb_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_ack_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_err_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_lock_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_rty_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_sel_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_we_o
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/m_stall_i
add wave -noupdate -group FIFO /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/transfer_done_i
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/VMEtoWB
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/WBtoVME
add wave -noupdate /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/s_VMEWriteInFifo
add wave -noupdate -radix unsigned /vme64x_tb/uut/Inst_VME64xCore_Top/Fifo/s_addr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {36265000 ps} 0}
configure wave -namecolwidth 184
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {36160167 ps} {36521200 ps}
hdl/boards/vfc/syn/VME64xTest.xise
View file @ f753f85e
This diff is collapsed.
hdl/vme64x-core/rtl/IRQ_Controller.vhd 0 → 100644
View file @ f753f85e
This diff is collapsed.
hdl/vme64x-core/rtl/SharedComps.vhd
View file @ f753f85e
......@@ -73,6 +73,31 @@ begin
end if;
end process;
end RTL;
--Register 32 bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Reg32bit is
port (
reset, clk_i, enable: in std_logic;
di : in std_logic_vector(31 downto 0);
do: out std_logic_vector(31 downto 0)
);
end Reg32bit;
architecture RTL of Reg32bit is
signal s_reg : std_logic_vector(31 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then s_reg <= (others => '0');
elsif enable = '1' then
s_reg <= di;
end if;
do <= s_reg;
end if;
end process;
end RTL;
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......
hdl/vme64x-core/rtl/VME64xCore_NoIpTop.vhd
View file @ f753f85e
This diff is collapsed.
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ f753f85e
......@@ -14,10 +14,10 @@ BIT_SET_CLR_REG => x"10", --Bit set register -- 0x10=module enable
USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER
FUNC0_ADER_0 =>x"A4", -- it was x"45"
FUNC0_ADER_1 =>x"c0",
FUNC0_ADER_0 =>x"08", -- it was x"45"
FUNC0_ADER_1 =>x"00",
FUNC0_ADER_2 =>x"00",
FUNC0_ADER_3 =>x"00", -- it was x"80"
FUNC0_ADER_3 =>x"c0", -- it was x"80"
FUNC1_ADER_0 =>x"00",
FUNC1_ADER_1 =>x"00",
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ f753f85e
......@@ -65,7 +65,7 @@ entity VME_bus is
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
-- CROM
CRaddr_o : out std_logic_vector(18 downto 0);
......@@ -96,12 +96,14 @@ entity VME_bus is
WBtoVME : out std_logic;
FifoMux : out std_logic;
-- IRQ controller signals
irqDTACK_i : in std_logic;
IACKinProgress_i : in std_logic;
IDtoData_i : in std_logic;
IRQlevelReg_o : out std_logic_vector(7 downto 0);
-- IRQ controller signals
--Int_CounttoData : out std_logic;
INT_Level : out std_logic_vector(7 downto 0);
INT_Vector : out std_logic_vector(7 downto 0);
--irqDTACK_i : in std_logic;
-- IACKinProgress_i : in std_logic;
--IDtoData_i : in std_logic;
-- IRQlevelReg_o : out std_logic_vector(7 downto 0);
-- Debug Davide
leds : out std_logic_vector(7 downto 0);
data_non_sampled : in std_logic_vector(63 downto 0);
......@@ -205,7 +207,7 @@ architecture RTL of VME_bus is
signal VME_DATA_oversampled : std_logic_vector(31 downto 0);
signal VME_AM_oversampled : std_logic_vector(5 downto 0);
signal VME_BBSY_n_oversampled : std_logic;
signal VME_IACKIN_n_oversampled : std_logic;
signal VME_IACK_n_oversampled : std_logic;
-- Bidirectional signals
signal s_VMEaddrInput : unsigned(31 downto 1);
......@@ -472,6 +474,7 @@ architecture RTL of VME_bus is
signal s_transfer_done_i : std_logic;
-- added by Davide for test:
signal s_counter : unsigned(31 downto 0);
signal s_countcyc : unsigned(9 downto 0);
signal s_error_CRCSR : std_logic;
signal s_BERR_out : std_logic; -- added by Davide --> for drive the VME_BERR_o when the VME_DTACK_o_n
signal s_errorflag : std_logic;
......@@ -490,6 +493,7 @@ architecture RTL of VME_bus is
signal s_memReqFlag : std_logic;
signal s_locDataSwap : std_logic_vector(63 downto 0);
signal s_locDataInSwap : std_logic_vector(63 downto 0);
signal s_numcyc : std_logic;
--signal s_AckIn : std_logic;
--signal s_wbData_sampled : std_logic_vector(63 downto 0);
begin
......@@ -600,14 +604,14 @@ begin
p_VMEmainFSM : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' or s_mainFSMreset = '1' or VME_IACKIN_n_oversampled = '0' then -- FSM is also reset on rising edge of address strobe (which indicates end of transfer) and on rising edge of block transfer limit signal
if s_reset = '1' or s_mainFSMreset = '1' or VME_IACK_n_oversampled = '0' then -- FSM is also reset on rising edge of address strobe (which indicates end of transfer) and on rising edge of block transfer limit signal
s_memReqFlag <= '0';
s_dtackOE <= '0';
s_dataDir <= '0';
s_dataDir <= '0';
--s_locAddr <= (others => '0'); --Added by Davide for read and write consecutively the same register in CSR
s_dataOE <= '1'; -- it was '0' changed by Davide
s_addrDir <= '0';
s_addrOE <= '1'; -- it was '0' changed by Davide
s_dataOE <= '0';
s_addrDir <= '0'; -- during IACK cycle the ADDR lines are input
s_addrOE <= '0';
s_mainDTACK <= '1'; -- it was 'Z'
s_memReq <= '0';
s_DSlatch <= '0';
......@@ -664,7 +668,7 @@ begin
s_berr <= '0';
transfer_done_flag <= '0';
s_BERR_out <= '0';
if s_VMEaddrLatch = '1' and VME_IACKIN_n_i = '1' then -- If address strobe goes low, check if this slave is addressed
if s_VMEaddrLatch = '1' and VME_IACK_n_i = '1' then -- If address strobe goes low, check if this slave is addressed
s_mainFSMstate <= DECODE_ACCESS; -- it was s_VMEaddrLatch = '1'; modified by Davide
else
s_mainFSMstate <= IDLE;
......@@ -1846,7 +1850,7 @@ begin
else
VME_DATA_b_o <= s_locDataSwap(31 downto 0); --std_logic_vector(s_locDataSwap(31 downto 0));
end if;
elsif IDtoData_i = '1' then
--elsif IDtoData_i = '1' then
-- VME_DATA_b_o <= "------------------------" & std_logic_vector(s_irqIDdata); --commented by Davide
-- else
-- VME_DATA_b_o <= (others => '0');
......@@ -2050,8 +2054,8 @@ begin
if s_resetAddrOffset = '1' or s_reset = '1' or s_mainFSMreset = '1' then
s_addrOffset <= (others => '0');
elsif s_incrementAddr = '1' then -- changed by Davide, it was s_incrementAddrPulse
if s_addressingType = TWOedge then
s_addrOffset <= s_addrOffset + 8;
--if s_addressingType = TWOedge then
-- s_addrOffset <= s_addrOffset + 8;
-- it was:
-- elsif s_typeOfDataTransfer = D08_0 then
-- if s_locAddrBeforeOffset(0) = '1' then
......@@ -2059,7 +2063,7 @@ begin
-- else
-- s_addrOffset <= s_addrOffset;
-- end if;
elsif s_typeOfDataTransfer = D08_0 or s_typeOfDataTransfer = D08_1 or s_typeOfDataTransfer = D08_2 or s_typeOfDataTransfer = D08_3 then
if s_typeOfDataTransfer = D08_0 or s_typeOfDataTransfer = D08_1 or s_typeOfDataTransfer = D08_2 or s_typeOfDataTransfer = D08_3 then
s_addrOffset <= s_addrOffset + 1;
-- it was:
--elsif s_typeOfDataTransfer = D16 then
......@@ -2874,7 +2878,9 @@ s_locData(63 downto 0) <= s_locDataOut(63 downto 0) sll to_integer(unsigned(s_D
-----------------------------------------------
end process;
-- modified by Davide:
IRQlevelReg_o <= (others => '0');
INT_Level <= std_logic_vector(s_CSRarray(IRQ_level));
INT_Vector <= std_logic_vector(s_CSRarray(IRQ_Vector));
--IRQlevelReg_o <= (others => '0');
--IRQlevelReg_o <= std_logic_vector(s_CSRarray(IRQ_level));
-- Initialization procedure
......@@ -3176,10 +3182,10 @@ s_locData(63 downto 0) <= s_locDataOut(63 downto 0) sll to_integer(unsigned(s_D
-- clk_i => clk_i
-- );
IACKINinputSample : SigInputSample
IACKinputSample : SigInputSample
port map(
sig_i => VME_IACKIN_n_i,
sig_o => VME_IACKIN_n_oversampled,
sig_i => VME_IACK_n_i,
sig_o => VME_IACK_n_oversampled,
clk_i => clk_i
);
-- ACKinputSample : FlipFlopD
......@@ -3232,7 +3238,7 @@ swapper_read: swapper PORT MAP(
leds(2) <= '0' when s_CSRarray(BIT_SET_CLR_REG)(3) = '1' else '1';
leds(7) <= s_counter(25);
leds(5) <= s_error_CRCSR;
leds(0) <= not s_debug1;
leds(0) <= not s_transferActive;
leds(1) <= not(s_func_sel(1));
leds(3) <= not s_debug3; --not(s_errorflagout);
leds(4) <= '1'; --s_errorflagout;
......@@ -3249,6 +3255,17 @@ swapper_read: swapper PORT MAP(
end if;
end if;
end process;
-- Counter for debugging the MBLT mode
process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' or s_mainFSMreset = '1' then s_countcyc <= (others => '0');
elsif s_numcyc = '1' then
s_countcyc <= s_countcyc + 1;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- process added by Davide for generate the error condition if block transfer overlap the limit
......@@ -3287,10 +3304,17 @@ s_rty2 <= not s_rty1;
-------------------------------------------
s_transfer_done_i <= transfer_done_i when s_FIFO = '1' else '1';
-- This process detect the access at the INT_COUNT register; location 0x00 in the WB RAM
--process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (b"000" & std_logic_vector(s_rel_locAddr(63 downto 3))) = (others => '0') and s_transferType = SINGLE and s_typeOfDataTransfer=D64 and s_mainDTACK = '0' and s_RW = '1' then
-- Int_CounttoData <= '1';
-- else
-- Int_CounttoData <= '0';
-- end if;
-- end if;
--end process;
--process added by Davide for Debug:
process(clk_i)
......@@ -3298,7 +3322,7 @@ process(clk_i)
if rising_edge(clk_i) then
if s_reset = '1' then s_debug1 <= '0';
elsif s_debug2 = '1' then
if(s_rel_locAddr = x"0000000000000000" and s_dataPhase = '1' and s_transferType = MBLT and VME_WRITE_n_oversampled = '1' and memAckWB_i = '1' and data_non_sampled = x"3132333435363730") then
if(s_dataPhase = '1' and s_transferType = MBLT and VME_WRITE_n_oversampled = '0' and s_mainDTACK = '0' and data_non_sampled /= s_locDataInSwap) then
s_debug1 <= '1';
end if;
end if;
......@@ -3311,7 +3335,8 @@ process(clk_i)
if rising_edge(clk_i) then
if s_reset = '1' then s_debug3 <= '0';
elsif s_debug4 = '1' then
if(s_rel_locAddr = x"0000000000000000" and s_dataPhase = '1' and s_transferType = MBLT and VME_WRITE_n_oversampled = '1' and s_mainDTACK = '0' and wbData_i = x"0000000000000000") then
if s_countcyc = 32 then
--if(s_dataPhase = '1' and s_transferType = MBLT and VME_WRITE_n_oversampled = '1' and s_mainDTACK = '0' and unsigned(data_non_sampled) /= s_locData) then --and s_rel_locAddr < 248) then
s_debug3 <= '1';
end if;
end if;
......@@ -3319,6 +3344,13 @@ process(clk_i)
end process;
s_debug4 <= not s_debug3;
DTACKfallingEdge : FallingEdgeDetection
port map (
sig_i => s_mainDTACK,
clk_i => clk_i,
FallEdge_o => s_numcyc
);
end RTL;
hdl/vme64x-core/rtl/VME_pack.vhd
View file @ f753f85e
......@@ -264,9 +264,9 @@ package VME_pack is
constant c_FUNC0_ADER_1_addr : unsigned(19 downto 0) := x"7FF6B";
constant c_FUNC0_ADER_2_addr : unsigned(19 downto 0) := x"7FF67";
constant c_FUNC0_ADER_3_addr : unsigned(19 downto 0) := x"7FF63";
constant c_IRQ_Vector_addr : unsigned(19 downto 0) := x"7FBFB";
constant c_IRQ_level_addr : unsigned(19 downto 0) := x"7FBF7";
constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FBF3";
constant c_IRQ_Vector_addr : unsigned(19 downto 0) := x"7FF5F";
constant c_IRQ_level_addr : unsigned(19 downto 0) := x"7FF5B";
constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FF53";
......
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