Interrupter working on the IRQ_i rising edge. A little change in the Cycle time…

Interrupter working on the IRQ_i rising edge. A little change in the Cycle time calculation. vme64x features unchanged git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@159 665b4545-5c6b-4c24-801b-41150b02b44b

Interrupter working on the IRQ_i rising edge. A little change in the Cycle time…
Interrupter working on the IRQ_i rising edge. A little change in the Cycle time calculation. vme64x features unchanged git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@159 665b4545-5c6b-4c24-801b-41150b02b44b
4f482126 · dpedrett · 8122815a · 4f482126 · 4f482126 · 4f482126
Commit 4f482126 authored Sep 18, 2012 by dpedrett
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Showing with 16 additions and 8 deletions

VME64xCore_Top.vhd hdl/vme64x-core/rtl/VME64xCore_Top.vhd +9 -1

VME_bus.vhd hdl/vme64x-core/rtl/VME_bus.vhd +4 -4

vme64x_pack.vhd hdl/vme64x-core/rtl/vme64x_pack.vhd +3 -3

No files found.
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -214,6 +214,7 @@
  signal s_time                    : std_logic_vector(39 downto 0);
  signal s_bytes                   : std_logic_vector(12 downto 0);
  signal s_W32                     : std_logic;
+  signal s_IRQ                     : std_logic;
  
  -- Oversampled input signals 
  signal VME_RST_n_oversampled     : std_logic;
@@ -337,6 +338,13 @@ begin
              clk_i => clk_i
            );			
 				
+  IrqrisingEdge : RisEdgeDetection
+  port map (
+              sig_i      => IRQ_i,
+              clk_i      => clk_i,
+              RisEdge_o  => s_IRQ
+          );
+				
  Inst_VME_bus: VME_bus 
  generic map(
              g_width      => c_width,
@@ -450,7 +458,7 @@ begin
         		 VME_ADDR_123      => VME_ADDR_oversampled(3 downto 1),
         		 INT_Level         => s_INT_Level,
         		 INT_Vector        => s_INT_Vector ,
-	          	 INT_Req           => IRQ_i,
+	          	 INT_Req           => s_IRQ,
 		          VME_IRQ_n_o       => s_VME_IRQ_n_o,
         		 VME_IACKOUT_n_o   => VME_IACKOUT_n_o,
         		 VME_DTACK_n_o     => s_VME_DTACK_IRQ,

--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -1647,16 +1647,16 @@ end process;
        if s_reset = '1' or s_mainFSMreset = '1' then 
           s_countertime <= (others => '0');
        elsif  VME_AS_n_i = '0' then
-           s_countertime <= s_countertime + unsigned(c_CLK_PERIOD);
+              s_countertime <= s_countertime + unsigned(c_CLK_PERIOD);
        end if;	
-  end if;
+     end if;
  end process;

  process(clk_i)
  begin
     if rising_edge(clk_i) then
        if (s_mainFSMreset = '1' and s_cardSel = '1') or s_reset = '1' then
-           s_time <= std_logic_vector(s_countertime);
+               s_time <= std_logic_vector(s_countertime + 30);
        end if;	
     end if;
  end process;                                                             
@@ -1736,7 +1736,7 @@ end process;
             FallEdge_o => s_VMEaddrLatch
          ); 	

-  RSTfallingEdge : RisEdgeDetection
+  RSTrisingEdge : RisEdgeDetection
  port map (
              sig_i      => s_reset,
              clk_i      => clk_i,

--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -61,17 +61,17 @@ package vme64x_pack is
  --_______________________________________________________________________________
  -- Constants:
  --WB data width:
-   constant c_width          : integer := 32; --must be 32 or 64!
+   constant c_width          : integer := 64; --must be 32 or 64!
 	--CRAM size in the CR/CSR space (bytes):
 	constant c_CRAM_SIZE      : integer := 1024; 
 	-- remember to set properly the "END_CRAM" register in the CR space
  -- WB addr width:
-	constant c_addr_width     : integer := 32;
+	constant c_addr_width     : integer := 10;
 	--
   constant DFS              : integer := 2;    -- for accessing at the ADEM's bit 2
   constant XAM_MODE         : integer := 0;  -- for accessing at the ADER's bit 0
 	-- Tclk in ns used to calculate the data transfer rate
-   constant c_CLK_PERIOD     : std_logic_vector(19 downto 0) := "00000000000000110010";
+   constant c_CLK_PERIOD     : std_logic_vector(19 downto 0) := "00000000000000001010";
  --AM table:
   constant c_A24_S_sup      : std_logic_vector(5 downto 0) := "111101";
   constant c_A24_S          : std_logic_vector(5 downto 0) := "111001";