Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
0b0209c1
Commit
0b0209c1
authored
Jan 28, 2020
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
top_tb: add a test for 2eSST.
parent
9388296e
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
86 additions
and
3 deletions
+86
-3
top_tb.vhd
hdl/testbench/simple_tb/top_tb.vhd
+86
-3
No files found.
hdl/testbench/simple_tb/top_tb.vhd
View file @
0b0209c1
...
@@ -30,7 +30,7 @@
...
@@ -30,7 +30,7 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
entity
top_tb
is
entity
top_tb
is
generic
(
g_SCENARIO
:
natural
range
0
to
9
:
=
6
);
generic
(
g_SCENARIO
:
natural
range
0
to
10
:
=
6
);
end
top_tb
;
end
top_tb
;
library
ieee
;
library
ieee
;
...
@@ -54,6 +54,7 @@ architecture behaviour of top_tb is
...
@@ -54,6 +54,7 @@ architecture behaviour of top_tb is
type
qword_array_t
is
array
(
natural
range
<>
)
of
qword_t
;
type
qword_array_t
is
array
(
natural
range
<>
)
of
qword_t
;
subtype
vme_am_t
is
std_logic_vector
(
5
downto
0
);
subtype
vme_am_t
is
std_logic_vector
(
5
downto
0
);
subtype
vme_xam_t
is
std_logic_vector
(
7
downto
0
);
function
hex1
(
v
:
std_logic_vector
(
3
downto
0
))
return
character
is
function
hex1
(
v
:
std_logic_vector
(
3
downto
0
))
return
character
is
begin
begin
...
@@ -284,10 +285,10 @@ begin
...
@@ -284,10 +285,10 @@ begin
g_END_SN
=>
x"000000"
,
g_END_SN
=>
x"000000"
,
g_decoder_0_adem
=>
x"ff000000"
,
g_decoder_0_adem
=>
x"ff000000"
,
g_decoder_0_amcap
=>
x"0000000
0
_0000ff00"
,
g_decoder_0_amcap
=>
x"0000000
1
_0000ff00"
,
g_decoder_0_dawpr
=>
x"84"
,
g_decoder_0_dawpr
=>
x"84"
,
g_decoder_1_adem
=>
x"fff80000"
,
g_decoder_1_adem
=>
x"fff80000"
,
g_decoder_1_amcap
=>
x"ff00000
0
_00000000"
,
g_decoder_1_amcap
=>
x"ff00000
1
_00000000"
,
g_decoder_1_dawpr
=>
x"84"
,
g_decoder_1_dawpr
=>
x"84"
,
g_decoder_2_adem
=>
x"00000000"
,
g_decoder_2_adem
=>
x"00000000"
,
g_decoder_2_amcap
=>
x"00000000_00000000"
,
g_decoder_2_amcap
=>
x"00000000_00000000"
,
...
@@ -757,6 +758,68 @@ begin
...
@@ -757,6 +758,68 @@ begin
read_release
;
read_release
;
end
read64_mblt
;
end
read64_mblt
;
procedure
read64_2esst
(
addr
:
std_logic_vector
(
31
downto
0
);
xam
:
vme_xam_t
;
variable
data
:
out
qword_array_t
)
is
variable
odd
:
boolean
;
begin
assert
addr
(
3
downto
0
)
=
"0000"
report
"unaligned read64_2e"
severity
error
;
assert
data
'length
mod
2
=
0
severity
error
;
-- Phase 1.
VME_LWORD_n_i
<=
xam
(
0
);
read_setup_addr
(
addr
(
31
downto
8
)
&
xam
(
7
downto
1
)
&
'0'
,
b"10_0000"
);
VME_DATA_i
<=
x"0000_0000"
;
VME_DS_n_i
<=
"10"
;
wait
until
(
VME_DTACK_OE_o
=
'1'
and
VME_DTACK_n_o
=
'0'
)
or
bus_timer
=
'1'
;
-- Phase 2.
VME_ADDR_i
<=
x"01"
&
x"00"
&
std_logic_vector
(
to_unsigned
(
data
'length
/
2
,
8
))
&
addr
(
7
downto
1
);
VME_DATA_i
<=
x"00_00_00_0"
&
x"0"
;
VME_LWORD_n_i
<=
addr
(
0
);
wait
for
5
ns
;
VME_DS_n_i
<=
"11"
;
wait
until
(
VME_DTACK_OE_o
=
'1'
and
VME_DTACK_n_o
=
'1'
)
or
bus_timer
=
'1'
;
-- Phase 3.
VME_ADDR_i
<=
(
others
=>
'0'
);
VME_DATA_i
<=
x"0000_0000"
;
wait
for
5
ns
;
VME_DS_n_i
<=
"10"
;
wait
until
(
VME_DTACK_OE_o
=
'1'
and
VME_DTACK_n_o
=
'0'
)
or
bus_timer
=
'1'
;
VME_DS_n_i
<=
"00"
;
odd
:
=
true
;
for
i
in
data
'range
loop
if
odd
then
wait
until
(
VME_DTACK_OE_o
=
'1'
and
VME_DTACK_n_o
=
'1'
)
or
bus_timer
=
'1'
;
else
wait
until
(
VME_DTACK_OE_o
=
'1'
and
VME_DTACK_n_o
=
'0'
)
or
bus_timer
=
'1'
;
end
if
;
odd
:
=
not
odd
;
data
(
i
)
:
=
VME_ADDR_o
&
VME_LWORD_n_o
&
VME_DATA_o
;
end
loop
;
-- 2eSST 2.8 Transfer termination
-- Transfers always terminate on an even beat.
--
-- The slave terminates a read transfer by stopping the
-- data transmission and then asserting RETRY*/RESP* and
-- BERR*.
wait
until
(
VME_BERR_n_o
=
'0'
and
VME_RETRY_n_o
=
'0'
and
VME_RETRY_OE_o
=
'1'
);
-- The master will respond by negating DS0*
VME_DS_n_i
<=
"11"
;
read_release
;
end
read64_2esst
;
procedure
write_setup_addr
(
addr
:
std_logic_vector
(
31
downto
0
);
procedure
write_setup_addr
(
addr
:
std_logic_vector
(
31
downto
0
);
lword_n
:
std_logic
;
lword_n
:
std_logic
;
am
:
vme_am_t
)
is
am
:
vme_am_t
)
is
...
@@ -1371,6 +1434,26 @@ begin
...
@@ -1371,6 +1434,26 @@ begin
report
"bad read at 000 (no AM decode)"
severity
error
;
report
"bad read at 000 (no AM decode)"
severity
error
;
end
if
;
end
if
;
when
10
=>
-- Test 2eSST
-- Set ADER
write8_conf
(
x"7_ff63"
,
x"64"
);
write8_conf
(
x"7_ff6f"
,
c_AM_2eVME_6U
&
"00"
);
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
read64_2esst
(
x"64_00_00_10"
,
c_XAM_A32_2ESST
,
v64
(
0
to
1
));
report
"at 04: "
&
hex8
(
v64
(
0
)(
63
downto
32
));
report
"at 05: "
&
hex8
(
v64
(
0
)(
31
downto
0
));
report
"at 06: "
&
hex8
(
v64
(
1
)(
63
downto
32
));
report
"at 07: "
&
hex8
(
v64
(
1
)(
31
downto
0
));
assert
v64
(
0
)
=
x"0000_0004_0000_0500"
and
v64
(
1
)
=
x"0006_0000_0700_0000"
report
"incorrect MBLT data 64"
severity
error
;
-- TODO: check IACK propagation.
-- TODO: check IACK propagation.
end
case
;
end
case
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment