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VME64x core
Commit 833193f0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl: some renaming in bridged mode: master -> SYS(FPGA), slave->APP(FPGA)

parent 48db76c6
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Showing with 30 additions and 287 deletions
hdl/rtl/Manifest.py
View file @ 833193f0
files = ["serial_bridge_master.vhd",
"serial_bridge_slave.vhd",
files = [
"serial_bridge_sys.vhd",
"serial_bridge_app.vhd",
#"vme64x_core.vhd",
"vme64x_pkg.vhd",
"vme_bus_bridge.vhd",
......@@ -9,12 +10,6 @@ files = ["serial_bridge_master.vhd",
"vme_irq_controller.vhd",
"vme_user_csr.vhd",
"xvme64x_bridge_serdes.vhd",
"xvme64x_core_master.vhd",
"xvme64x_core_slave.vhd",
"xvme64x_core.vhd"];
if (target == "xilinx" and syn_device[0:4].upper()=="XC6S"):
files.append( "platform/bridge_serdes_spartan6.vhd" )
elif (target == "xilinx" and syn_device[0:4].upper()=="XC7K"):
files.append( "platform/bridge_serdes_kintex7.vhd" )
\ No newline at end of file
"xvme64x_core_app.vhd",
"xvme64x_core_sys.vhd",
"xvme64x_core.vhd"];
\ No newline at end of file
hdl/rtl/platform/bridge_serdes_kintex7.vhd
View file @ 833193f0
......@@ -8,7 +8,7 @@ use unisim.vcomponents.all;
entity bridge_serdes_kintex7 is
generic (
g_mode : t_bridge_serdes_mode := MASTER;
g_mode : t_bridge_serdes_mode := SYS_FPGA;
g_SERDES_RX_DELAY_TAPS : integer := 0;
g_CLOCK_PERIOD : integer := 16;
g_use_idelay :boolean := false
......@@ -98,7 +98,7 @@ begin
clk_125m_0 <= clk_125m_i;
clk_500m_180 <= not clk_500m_0;
gen1 : if g_mode = MASTER generate
gen1 : if g_mode = SYS_FPGA generate
U_clk_buf : IBUFGDS
generic map (
......@@ -115,7 +115,7 @@ begin
end generate gen1;
gen2 : if g_mode /= MASTER generate
gen2 : if g_mode /= SYS_FPGA generate
ser_clk_buf <= clk_125m_i;
end generate gen2;
......@@ -375,7 +375,7 @@ begin
end generate gen_serdeses;
gen3 : if g_mode = SLAVE generate
gen3 : if g_mode = APP_FPGA generate
OBUFDS_clk : OBUFDS
......
hdl/rtl/platform/bridge_serdes_spartan6.vhd
View file @ 833193f0
......@@ -10,7 +10,7 @@ use work.gencores_pkg.all;
entity bridge_serdes_spartan6 is
generic (
g_mode : t_bridge_serdes_mode := MASTER;
g_mode : t_bridge_serdes_mode := SYS_FPGA;
g_SERDES_RX_DELAY_TAPS : integer:= 0;
g_CLOCK_PERIOD : integer := 16
);
......@@ -278,7 +278,7 @@ begin
io_reset <= not rst_n_i;
gen1 : if g_mode = MASTER generate
gen1 : if g_mode = SYS_FPGA generate
U_clk_buf : IBUFGDS
generic map (
......@@ -309,7 +309,7 @@ begin
end generate gen1;
gen2 : if g_mode /= MASTER generate
gen2 : if g_mode /= SYS_FPGA generate
ser_clk_buf <= clk_125m_i;
end generate gen2;
......@@ -569,7 +569,7 @@ gen_clk_62m5 : if g_CLOCK_PERIOD = 16 generate
end generate gen_serdeses;
gen3: if g_mode = SLAVE generate
gen3: if g_mode = APP_FPGA generate
-- cmp_oserdes_clk : OSERDES2
-- generic map (
-- DATA_RATE_OQ => "SDR",
......
hdl/rtl/serial_bridge_slave.vhd → hdl/rtl/serial_bridge_app.vhd
View file @ 833193f0
......@@ -34,7 +34,7 @@ use work.wishbone_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity serial_bridge_slave is
entity serial_bridge_app is
generic (
g_CLOCK_PERIOD : integer
);
......@@ -97,9 +97,9 @@ entity serial_bridge_slave is
heartbeat_rx_o : out std_logic
);
end serial_bridge_slave;
end serial_bridge_app;
architecture rtl of serial_bridge_slave is
architecture rtl of serial_bridge_app is
constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0";
constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1";
......
hdl/rtl/serial_bridge_master.vhd → hdl/rtl/serial_bridge_sys.vhd
View file @ 833193f0
......@@ -8,7 +8,7 @@ use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity serial_bridge_master is
entity serial_bridge_sys is
generic(
g_clock_period : integer
);
......@@ -66,9 +66,9 @@ entity serial_bridge_master is
heartbeat_rx_o : out std_logic
);
end serial_bridge_master;
end serial_bridge_sys;
architecture rtl of serial_bridge_master is
architecture rtl of serial_bridge_sys is
constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0";
constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1";
......
hdl/rtl/vme64x_pkg.vhd
View file @ 833193f0
......@@ -43,7 +43,7 @@ package vme64x_pkg is
-- Constants
------------------------------------------------------------------------------
type t_BRIDGE_SERDES_MODE is ( MASTER, SLAVE );
type t_BRIDGE_SERDES_MODE is ( SYS_FPGA, APP_FPGA );
-- Manufactuer IDs.
constant c_CERN_ID : std_logic_vector(23 downto 0) := x"080030";
......
hdl/rtl/vme_sfpga_bridge.vhd deleted 100644 → 0
View file @ 48db76c6
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity bridge_master is
generic(
g_clock_period : integer
);
port (
afpga_rst_n_i : in std_logic;
afpga_clk_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_o : out std_logic;
mem_req_i : in std_logic;
mem_is_blt_i : in std_logic;
mem_ack_o : out std_logic;
mem_err_o : out std_logic;
mem_we_i : in std_logic;
mem_addr_i : in std_logic_vector(31 downto 0);
mem_data_o : out std_logic_vector(31 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_sel_i : in std_logic_vector(3 downto 0);
-- Function decoder
addr_decoder_i : in std_logic_vector(31 downto 1);
addr_decoder_o : out std_logic_vector(31 downto 1);
decode_start_i : in std_logic;
decode_done_o : out std_logic;
am_i : in std_logic_vector( 5 downto 0);
decode_sel_o : out std_logic;
-- CR/CSR space signals:
cr_csr_addr_i : in std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_i : in std_logic;
cr_csr_req_i : in std_logic;
1 cr_csr_done_o : out std_logic;
module_enable_o : out std_logic;
bar_o : out std_logic_vector( 4 downto 0);
-- Interrupts
int_level_o : out std_logic_vector( 2 downto 0);
int_vector_o : out std_logic_vector( 7 downto 0);
irq_pending_o : out std_logic;
irq_ack_i : in std_logic
);
end bridge_master;
architecture rtl of bridge_master is
constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0";
constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1";
constant c_tag_config : std_logic_vector(3 downto 0) := x"2";
constant c_tag_decode_req : std_logic_vector(3 downto 0) := x"2";
constant c_tag_read_cpl : std_logic_vector(3 downto 0) := x"3";
constant c_tag_irq : std_logic_vector(3 downto 0) := x"4";
constant c_tag_iackin : std_logic_vector(3 downto 0) := x"5";
constant c_tag_iackout : std_logic_vector(3 downto 0) := x"6";
constant c_tag_aux : std_logic_vector(3 downto 0) := x"7";
signal afpga_dout : std_logic_vector(15 downto 0);
signal afpga_din : std_logic_vector(15 downto 0);
signal afpga_frame_out : std_logic;
signal afpga_frame_in : std_logic;
signal afpga_clk_n : std_logic;
type t_state is
(
IDLE, TX_CSR_REQ,
RX_CSR_ACK );
type t_rx_state is
(
IDLE,
RX_CONF0
);
signal state : t_state;
signal rx_state : t_state;
begin
afpga_clk_n <= not afpga_clk_i;
gen_ddr_ios : for i in 0 to 7 generate
U_ODDR_Data : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_d_o(i),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_dout(2*i),
D1 => afpga_dout(2*i+1),
R => '0',
S => '0');
U_IDDR_Data : IDDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q0 => afpga_din(2*i+1),
Q1 => afpga_din(2*i),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_d_i(i),
R => '0',
S => '0');
end generate gen_ddr_ios;
U_IDDR_Frame : IDDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q0 => afpga_frame_in,
Q1 => open,
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_frame_i,
R => '0',
S => '0');
U_ODDR_Frame : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_frame_o,
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '0',
D0 => afpga_frame_out,
D1 => afpga_frame_out,
R => '0',
S => '0');
p_in_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
rx_state <= IDLE;
else
case rx_state is
when IDLE =>
if afpga_frame_in = '1' then
case afpga_din(15 downto 12) is
when c_tag_config =>
module_enable_o <= afpga_din(11);
bar_o <= afpga_din(10 downto 6);
rx_state <= RX_CONF0;
when others => null;
end case;
end if;
when RX_CONF0 =>
int_level_o <= afpga_din(2 downto 0);
int_vector_o <=afpga_din(15 downto 8);
irq_pending_o <= afpga_din(3);
rx_state <= IDLE;
end case;
end if;
end if;
end process;
p_out_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
state <= IDLE;
afpga_frame_out <= '0';
else
case state is
when IDLE =>
cr_csr_done_o <= '0';
afpga_frame_out <= '0';
if cr_csr_req_i = '1' then
afpga_frame_out <= '1';
afpga_dout <= c_tag_csr_req & cr_csr_we_i & cr_csr_addr_i(18 downto 5);
state <= TX_CSR_REQ;
end if;
if decode_start_i = '1' then
afpga_frame_out <= '1';
afpga_dout <= c_tag_decode_req & am_i & "000000";
state <= TX_DECODE_REQ0;
end if;
when TX_CSR_REQ =>
afpga_frame_out <= '0';
afpga_dout <= cr_csr_addr_i(4 downto 0) & "000" & cr_csr_data_i;
state <= RX_CSR_ACK;
when RX_CSR_ACK =>
if afpga_frame_in = '1' and afpga_din(15 downto 12) = c_tag_csr_rsp then
cr_csr_done_o <= '1';
cr_csr_data_o <= afpga_din(7 downto 0);
state <= IDLE;
end if;
when TX_DECODE_REQ0 =>
afpga_dout <= addr_decoder_i(31 downto 16);
state <= TX_DECODE_REQ1;
when TX_DECODE_REQ1 =>
afpga_dout <= addr_decoder_i(15 downto 1) & '0';
state <= TX_DECODE_REQ1;
when RX_DECODE_RSP =>
end case;
end if;
end if;
end process;
end rtl;
hdl/rtl/xvme64x_bridge_serdes.vhd
View file @ 833193f0
......@@ -8,7 +8,7 @@ use unisim.vcomponents.all;
entity xvme64x_bridge_serdes is
generic (
g_mode : t_bridge_serdes_mode := MASTER;
g_mode : t_bridge_serdes_mode := SYS_FPGA;
g_platform : string := "spartan6";
g_SERDES_RX_DELAY_TAPS : integer:= 0;
g_CLOCK_PERIOD : integer := 16
......
hdl/rtl/xvme64x_core_slave.vhd → hdl/rtl/xvme64x_core_app.vhd
View file @ 833193f0
......@@ -39,7 +39,7 @@ use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
entity xvme64x_core_slave is
entity xvme64x_core_app is
generic (
-- Clock period (ns). Used for DS synchronization. A value is required.
g_CLOCK_PERIOD : natural;
......@@ -145,9 +145,9 @@ entity xvme64x_core_slave is
heartbeat_rx_o : out std_logic
);
end xvme64x_core_slave;
end xvme64x_core_app;
architecture rtl of xvme64x_core_slave is
architecture rtl of xvme64x_core_app is
-- Compute the index of the last function decoder used. Assume sequential
-- use of decoders (ie decoders 0 to N - 1 are used, and decoders N to 7
......@@ -277,7 +277,7 @@ begin
s_reset_n <= rst_n_i;
inst_serial_bridge : entity work.serial_bridge_slave
inst_serial_bridge : entity work.serial_bridge_app
generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD)
port map (
......
hdl/rtl/xvme64x_core_master.vhd → hdl/rtl/xvme64x_core_sys.vhd
View file @ 833193f0
......@@ -38,7 +38,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pkg.all;
entity xvme64x_core_master is
entity xvme64x_core_sys is
generic (
-- Clock period (ns). Used for DS synchronization. A value is required.
g_CLOCK_PERIOD : natural
......@@ -62,9 +62,9 @@ entity xvme64x_core_master is
heartbeat_tx_o : out std_logic
);
end xvme64x_core_master;
end xvme64x_core_sys;
architecture rtl of xvme64x_core_master is
architecture rtl of xvme64x_core_sys is
signal s_reset_n : std_logic;
......@@ -267,7 +267,7 @@ begin
s_ga <= not vme_i.ga(4 downto 0) when s_ga_parity = '1' else '1' & x"e";
inst_serial_bridge: entity work.serial_bridge_master
inst_serial_bridge: entity work.serial_bridge_sys
generic map (
g_clock_period => g_clock_period)
port map (
......
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