- Dec 07, 2020
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Tristan Gingold authored
Dab64x shared vme See merge request !4
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Mathieu Saccani authored
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Mathieu Saccani authored
Expose card_sel signal at the top of vme_bus module (for shared VME on Dab64x board). Leave it open in the upper blocks if unused.
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- Oct 16, 2020
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Tristan Gingold authored
Fix verilog wrapper See merge request !3
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- Aug 05, 2020
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Tom Levens authored
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Tom Levens authored
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- Jul 20, 2020
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Tristan Gingold authored
VME Core 64x wrapper for Verilog instantiation. See merge request !2
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Mathieu Saccani authored
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Tristan Gingold authored
Change the generic assignment per index/field in a record type, because it is… See merge request !1
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Mathieu Saccani authored
Change the generic assignment per index/field in a record type, because it is not compatible with some synthesizers (Synplify for instance).
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- Jun 04, 2020
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Tristan Gingold authored
Use transfer rate to select number of cycles for setup and hold. Prefetch earlier.
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Tristan Gingold authored
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- Apr 24, 2020
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Tristan Gingold authored
In the previous code, a function that is selected but not supported for the AM was masking any following function.
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
And wait until WB transfers are done before accepting a new VME transaction.
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- Apr 14, 2020
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Tristan Gingold authored
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