vme_cr_csr_space.vhd: minor refactoring.

hdl/rtl/vme_cr_csr_space.vhd

@@ -190,11 +190,9 @@ architecture rtl of vme_cr_csr_space is
   -- CRAM
   type t_cram is array (c_CRAM_SIZE-1 downto 0) of std_logic_vector(7 downto 0);
 
-  signal s_cram             : t_cram;
   signal s_cram_data        : std_logic_vector(7 downto 0);
   signal s_cram_waddr       : unsigned(18 downto 2);
   signal s_cram_raddr       : unsigned(18 downto 2);
-  signal s_cram_we          : std_logic;
 
   -- Addresses
   subtype crcsr_addr is unsigned(18 downto 2);
@@ -507,6 +505,9 @@ begin
   -- CRAM
   ------------------------------------------------------------------------------
   gen_cram_ena: if c_CRAM_ENA = true generate
+    signal s_cram    : t_cram;
+    signal s_cram_we : std_logic;
+  begin
     s_cram_access <= '1' when s_addr >= c_BEG_CRAM and
                               s_addr <= c_END_CRAM
                          else '0';