Fix wrong end entity name

hdl/rtl/vme64x_core_verilog.vhd

@@ -100,7 +100,7 @@ entity vme64x_core_verilog is
       return BYTE ;
     end if;
   end string_to_wb_grn ;
-end vme64x_core_wrap;
+end vme64x_core_verilog;
 
 architecture wrapper of vme64x_core_verilog  is
 begin