- 08 Jul, 2021 5 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 07 Jul, 2021 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 22 Mar, 2021 6 commits
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Federico Vaga authored
2.0.3 - 2021-03-22 ================== Fixed ----- - sw: fix SVEC flasher size
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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Juan David Gonzalez Cobas authored
Being stabic is no excuse for not looking twice, David :D. Reported-by: Rene Geissler <R.Geissler@gsi.de>
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Juan David Gonzalez Cobas authored
Reported-by: Rene Geissler <R.Geissler@gsi.de>
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- 16 Mar, 2021 4 commits
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Federico Vaga authored
2.0.2 - 2021-03-16 ================== Changed ------- - sw: better version validation implementation
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The code was checking for the exact match MAJ.MIN, but what we want is: REAL CMP EXPECTED ---- --- -------- MAJ == MAJ MIN >= MIN Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 08 Feb, 2021 7 commits
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Federico Vaga authored
2.0.1 - 2021-02-08 ================== Added ----- - sw: dynamically set the compatibility version between software and FPGA - sw: added the possibility to ignore the version check Changed ------- - hdl: the DMA interface changed to support BLT and MBLT acquisitions
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Tristan Gingold authored
The memory map of the svec base is therefore changed.
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Tristan Gingold authored
so that it properly computes dependencies
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Federico Vaga authored
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- 02 Feb, 2021 2 commits
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Tristan Gingold authored
The memory map of the svec base is therefore changed.
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Tristan Gingold authored
so that it properly computes dependencies
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- 05 Jan, 2021 6 commits
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Federico Vaga authored
1.5.2 - 2020-11-24 ================== Added ----- - sw: tool to inspect SVEC bitstream ROM Fixed ----- - hdl: svec-base version
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 26 Nov, 2020 3 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 24 Nov, 2020 5 commits
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Federico Vaga authored
1.5.1 - 2020-11-24 ================== Fixed ----- - sw: NULL pointer at load time when using the SPI controller - sw: remove old unload procedure that causes BUG_ON to be triggered without valid reasons
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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