Merge branch 'feature/dma-page' into develop

ad25e124 · Federico Vaga · 8d66ebf1 · 4f3c6cb4 · ad25e124 · ad25e124
Commit ad25e124 authored Feb 08, 2021 by Federico Vaga
4 changed files
--- a/hdl/rtl/svec_base_regs.cheby
+++ b/hdl/rtl/svec_base_regs.cheby
 memory-map:
  name: svec_base_regs
  bus: wb-32-be
-  size: 0x2000
+  size: 0x4000
  children:
    - submap:
        name: metadata
@@ -74,17 +74,6 @@ memory-map:
          x-hdl:
            type: wire
            write-strobe: True
-       - reg:
-          name: ddr4_data
-          description: data to read or to write in ddr4
-          access: rw
-          width: 32
-          x-hdl:
-            type: wire
-            read-strobe: True
-            write-strobe: True
-            read-ack: True
-            write-ack: True
       - reg:
          name: ddr5_addr
          description: address of data to read or to write
@@ -93,17 +82,6 @@ memory-map:
          x-hdl:
            type: wire
            write-strobe: True
-       - reg:
-          name: ddr5_data
-          description: data to read or to write in ddr5
-          access: rw
-          width: 32
-          x-hdl:
-            type: wire
-            read-strobe: True
-            write-strobe: True
-            read-ack: True
-            write-ack: True
    - submap:
        name: therm_id
        description: Thermometer and unique id
@@ -139,6 +117,7 @@ memory-map:
    - submap:
        name: buildinfo
        description: a ROM containing build information
+        address: 0x200
        size: 0x100
        interface: sram
    - submap:
@@ -146,6 +125,22 @@ memory-map:
        address: 0x1000
        description: white-rabbit core registers
        comment: In particular, the vuart is at 0x1500
+        size: 0x800
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: ddr4_data
+        description: DMA page for ddr4
+        address: 0x2000
+        size: 0x1000
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: ddr5_data
+        description: DMA page for ddr5
+        address: 0x3000
        size: 0x1000
        interface: wb-32-be
        x-hdl:

--- a/hdl/rtl/svec_base_regs.vhd
+++ b/hdl/rtl/svec_base_regs.vhd
--- a/hdl/rtl/svec_base_wr.vhd
+++ b/hdl/rtl/svec_base_wr.vhd
--- a/hdl/syn/common/svec_base_common.ucf
+++ b/hdl/syn/common/svec_base_common.ucf
@@ -234,15 +234,15 @@ TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";

 NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";

-TIMESPEC TS_ref_sync_ffs  = FROM ref_clk TO "sys_sync_ffs"  TIG;
-TIMESPEC TS_sys_sync_ffs  = FROM sys_clk TO "sys_sync_ffs"  TIG;
+#TIMESPEC TS_ref_sync_ffs  = FROM ref_clk TO "sys_sync_ffs"  TIG;
+#TIMESPEC TS_sys_sync_ffs  = FROM sys_clk TO "sys_sync_ffs"  TIG;

 # Exceptions for crossings via gc_sync_register

 NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";

-TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
-TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
+#TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
+#TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";

-TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg"  8ns  DATAPATHONLY;
-TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg"  16ns DATAPATHONLY;
+#TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg"  8ns  DATAPATHONLY;
+#TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg"  16ns DATAPATHONLY;