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Last edited by Erik van der Bij

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Simple VME FMC Carrier (SVEC)

Project description

The FMC VME Carrier is an FMC carrier in VME64x format that can hold two FMC cards and an SFP connector. The FMC mezzanine slots use low-pin count (LPC) connectors. This board is optimised for cost and will be usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay).

Other FMC projects and the FMC standard are described in FMC Projects.


SVEC V1 production board - block diagram

Main Features

  • VME64x interface
  • Two Low-Pin Count FMC slots
    • Vadj fixed to 2.5V
    • No dedicated clock signals from Carrier to FMC (as only available on HPC pins and use LPC)
    • FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
  • Xilinx FPGAs
    • Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
      • Direct connection to all resources such as VME64x, memories and FMC connectors
    • System FPGA: Spartan-6 XC6SLX9-2FTG256C
      • Provides VME bootloader, early oscillator/PLL config
      • Configuration Flash memory for both Main FPGA and Application FPGA configuration
  • FPGA configuration
    • From SPI flash or via VME
  • Clocking resources
    • 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
    • 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
    • 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
    • 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
  • On-board memories
    • 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16JT-125)
    • 1x 128 Mbit SPI flash for FPGA firmware storage (MT25QL128ABA1EW9-0SIT, select N25Q128 in IMPACT)
    • 64kbit EEPROM connected for storing application parameters (24AA64T-I/MC)
    • 1x I2C configuration EEPROM (24LC64)
  • Miscellaneous
    • On-board thermometer IC (DS18B20U+)
    • Unique 64-bit identifier (DS18B20U+)
  • Front panel
    • 1x SFP port (White Rabbit compatible)
    • 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
    • 2x mini displayPort connectors for high-speed serial GTP links (not for video)
    • 8x Programmable LED
    • Reset push button
  • Internal connectors
    • VME P2 connector provides access to a Rear Transition Module (compatible to VFC)
      • 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS pairs) connected to the Application FPGA
      • 2x 125 MHz LVDS clocks provided to the RTM
    • Xilinx-style JTAG connector
    • Internal mini USB 2.0 High Speed connector for stand-alone applications (CP2103)
  • Optional features, check with vendor
    • Internal 2 x SATA connector for stand-alone PCI Express connectivity (clock + data)
    • Internal 4 x UFL connectors with low-jitter clock for FMC cards
    • Internal additional USB 2.0 on 4-pin header (FT2232HL)
    • Battery for secure storage of FPGA configuration data
    • Stand-alone features
      • External supply connector (3.3V, 5V) on internal SATA connector
      • Optional 3.3V adapter PCB to make the SVEC work in classic non-VME64x crates.
      • PCIe interface on internal SATA connector
  • 10-layer PCB

Project information

Releases

Latest:*

All Gateware releases:* See the Releases page.

Contacts

Commercial producers

General question about project

Status

Date Event
01-07-2011 First ideas for starting this simpler and cheaper version of the FMC VME Carrier.
19-07-2011 Main features specification written.
25-10-2011 Order sent out to a company for the schematics design.
02-05-2012 V0 files created. Ordered 4 assembled boards.
05-06-2012 V1: replace eSATA by microHDMI, remove front USB (space reasons).
15-06-2012 Four V0 boards received at CERN.
21-06-2012 V0: VME works, bootloader works, White Rabbit works, FMC slots work (two Fine Delay cards operating correctly)
04-09-2012 V1 of design released. Ordered 9. Price Enquiry for production of 90 will follow soon.
24-10-2012 Four V1 boards received.
01-11-2012 V2 design files released. Minor corrections on mechanics and one electrical issue.
05-11-2012 90 boards ordered. 30 for delivery end January 2013, 60 for end March 2013.
08-02-2013 30 V1-0 boards received at CERN.
17-07-2013 10 V2-0 pre-series boards received.
31-07-2013 28 additional board ordered.
09-10-2013 50 V2-0 series boards received.
08-11-2013 28 V2-0 series boards received (in total 118 received).
05-12-2013 Hardware manual written by Janz Tec.
02-04-2014 Release 2.0 of the SVEC standard gateware (bootloader & golden) is available
20-10-2014 V3-0 released. Changes can be seen in Roadmap
26-11-2014 Release 3.0 of the SVEC bootloader is available
17-05-2018 240 V3-0 boards ordered by CERN.
17-05-2018 240 V3-0 boards ordered by CERN, delivered on 17-12-2018.
13-06-2019 Will design a new board SVEC7 with DDR3 SIM memory (higher bandwidth), another FPGA and resolving certain obsolescence issues
25-10-2021 New board project SVEC7 on hold for a year.
06-03-2024 No plans to make a new design. No plans for new productions. Project end.
09-08-2024 CERN purchased the last SVECs that were in stock at the commercial producer Janz Tec.

Complete status

Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 9 August 2024