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Simple VME FMC Carrier SVEC
Commits
577b31c8
Commit
577b31c8
authored
Feb 08, 2021
by
Federico Vaga
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Merge branch 'release/v2.0.1' into master
parents
c15d15c7
6fe71827
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8 changed files
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497 additions
and
496 deletions
+497
-496
CHANGELOG.rst
CHANGELOG.rst
+11
-0
svec_base_regs.cheby
hdl/rtl/svec_base_regs.cheby
+18
-23
svec_base_regs.vhd
hdl/rtl/svec_base_regs.vhd
+393
-339
svec_base_wr.vhd
hdl/rtl/svec_base_wr.vhd
+55
-124
svec_base_common.ucf
hdl/syn/common/svec_base_common.ucf
+6
-6
svec.h
software/include/uapi/linux/svec.h
+0
-1
Kbuild
software/kernel/Kbuild
+4
-1
svec-core-fpga.c
software/kernel/svec-core-fpga.c
+10
-2
No files found.
CHANGELOG.rst
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577b31c8
...
...
@@ -2,6 +2,17 @@
Change Log
==========
2.0.1 - 2021-02-08
==================
Added
-----
- sw: dynamically set the compatibility version between software and FPGA
- sw: added the possibility to ignore the version check
Changed
-------
- hdl: the DMA interface changed to support BLT and MBLT acquisitions
1.5.2 - 2020-11-24
==================
Added
...
...
hdl/rtl/svec_base_regs.cheby
View file @
577b31c8
memory-map:
name: svec_base_regs
bus: wb-32-be
size: 0x
2
000
size: 0x
4
000
children:
- submap:
name: metadata
...
...
@@ -74,17 +74,6 @@ memory-map:
x-hdl:
type: wire
write-strobe: True
- reg:
name: ddr4_data
description: data to read or to write in ddr4
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- reg:
name: ddr5_addr
description: address of data to read or to write
...
...
@@ -93,17 +82,6 @@ memory-map:
x-hdl:
type: wire
write-strobe: True
- reg:
name: ddr5_data
description: data to read or to write in ddr5
access: rw
width: 32
x-hdl:
type: wire
read-strobe: True
write-strobe: True
read-ack: True
write-ack: True
- submap:
name: therm_id
description: Thermometer and unique id
...
...
@@ -139,6 +117,7 @@ memory-map:
- submap:
name: buildinfo
description: a ROM containing build information
address: 0x200
size: 0x100
interface: sram
- submap:
...
...
@@ -146,6 +125,22 @@ memory-map:
address: 0x1000
description: white-rabbit core registers
comment: In particular, the vuart is at 0x1500
size: 0x800
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ddr4_data
description: DMA page for ddr4
address: 0x2000
size: 0x1000
interface: wb-32-be
x-hdl:
busgroup: True
- submap:
name: ddr5_data
description: DMA page for ddr5
address: 0x3000
size: 0x1000
interface: wb-32-be
x-hdl:
...
...
hdl/rtl/svec_base_regs.vhd
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577b31c8
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hdl/rtl/svec_base_wr.vhd
View file @
577b31c8
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hdl/syn/common/svec_base_common.ucf
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577b31c8
...
...
@@ -234,15 +234,15 @@ TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
#
TIMESPEC TS_ref_sync_ffs = FROM ref_clk TO "sys_sync_ffs" TIG;
#
TIMESPEC TS_sys_sync_ffs = FROM sys_clk TO "sys_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
#
TIMEGRP "ref_sync_reg" = "sync_reg" EXCEPT "ref_clk";
#
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
#
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "ref_sync_reg" 8ns DATAPATHONLY;
#
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
software/include/uapi/linux/svec.h
View file @
577b31c8
...
...
@@ -21,7 +21,6 @@
#define SVEC_META_BOM_END_MASK 0xFFFF0000
#define SVEC_META_BOM_VER_MASK 0x0000FFFF
#define SVEC_META_VERSION_MASK 0xFFFF0000
#define SVEC_META_VERSION_1_4 0x01040000
#ifndef BIT
#define BIT(_b) (1 << _b)
...
...
software/kernel/Kbuild
View file @
577b31c8
...
...
@@ -8,9 +8,12 @@ endif
# add versions of used submodules
VER_MAJ := $(shell echo $(subst v,,$(VERSION)) | cut -d '.' -f 1)
VER_MIN := $(shell echo $(subst v,,$(VERSION)) | cut -d '.' -f 2)
SVEC_META_VERSION_COMPAT := $(shell printf "0x%02x%02x0000" $(VER_MAJ) $(VER_MIN))
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DVERSION=\"$(VERSION)\"
ccflags-y += -DSVEC_META_VERSION_COMPAT=$(SVEC_META_VERSION_COMPAT)
ccflags-y += -Wall -Werror
ccflags-y += -I$(VMEBRIDGE_ABS)/include
...
...
software/kernel/svec-core-fpga.c
View file @
577b31c8
...
...
@@ -18,6 +18,11 @@
#include "svec.h"
#include "svec-core-fpga.h"
static
int
version_ignore
=
0
;
module_param
(
version_ignore
,
int
,
0644
);
MODULE_PARM_DESC
(
version_ignore
,
"Ignore the version declared in the FPGA and force the driver to load all components (default 0)"
);
enum
svec_fpga_irq_lines
{
SVEC_FPGA_IRQ_FMC_I2C
=
0
,
SVEC_FPGA_IRQ_SPI
,
...
...
@@ -830,12 +835,15 @@ static bool svec_fpga_is_valid(struct svec_dev *svec_dev,
return
false
;
}
if
((
meta
->
version
&
SVEC_META_VERSION_MASK
)
!=
SVEC_META_VERSION_1_4
)
{
if
(
!
version_ignore
&&
(
meta
->
version
&
SVEC_META_VERSION_MASK
)
!=
SVEC_META_VERSION_COMPAT
)
{
dev_err
(
&
svec_dev
->
dev
,
"Unknow version: %08x
\n
"
,
meta
->
version
);
"Unknow version: %08x, expected: %08x
\n
"
,
meta
->
version
,
SVEC_META_VERSION_COMPAT
);
return
false
;
}
return
true
;
}
...
...
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