Commit df883e77 authored by Federico Vaga's avatar Federico Vaga

sw: on loader error report CSR value

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent e39fec66
......@@ -414,12 +414,12 @@ static int svec_fpga_write_stop(struct fpga_manager *mgr,
}
if (!(rval & XLDR_CSR_DONE)) {
dev_err(&mgr->dev, "error: FPGA program timeout.\n");
dev_err(&mgr->dev, "error: FPGA program timeout {csr: 0x%08x}.\n", rval);
err = -EIO;
}
if (rval & XLDR_CSR_ERROR) {
dev_err(&mgr->dev, "Bitstream loaded, status ERROR\n");
dev_err(&mgr->dev, "Bitstream loaded, status ERROR {csr: 0x%08x}\n", rval);
err = -EINVAL;
}
out:
......
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