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Simple VME FMC Carrier SVEC
Commit b18c0b5a authored by Federico Vaga's avatar Federico Vaga
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sw:drv: isolate unlock function, and check activation on reset 

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 74f73fb3
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Showing with 19 additions and 17 deletions
software/kernel/svec-core.c
View file @ b18c0b5a
......@@ -214,15 +214,12 @@ static void svec_dbg_exit(struct svec_dev *svec_dev)
debugfs_remove_recursive(svec_dev->dbg_dir);
}
/**
/*
* Writes a "magic" unlock sequence, activating the System FPGA bootloader
* regardless of what is going on in the Application FPGA. This clears
* the Application FPGA as well by resetting the FPGA chip.
* @svec a valid SVEC device instance
* Return: 0 on success, otherwise a negative errno number
*/
static int svec_fpga_reset(struct fpga_manager *mgr)
static void svec_fpga_loader_unlock(struct fpga_manager *mgr)
{
struct svec_dev *svec = mgr->priv;
struct vme_dev *vdev = to_vme_dev(svec->dev.parent);
......@@ -234,11 +231,8 @@ static int svec_fpga_reset(struct fpga_manager *mgr)
loader_addr + XLDR_REG_BTRIGR);
mdelay(1);
}
return 0;
}
/**
* Checks if the SVEC is in bootloader mode. If true, it implies that
* the Appliocation FPGA has no bitstream loaded.
......@@ -267,6 +261,22 @@ static int svec_fpga_loader_is_active(struct fpga_manager *mgr)
return (strncmp(buf, "SVEC", 4) == 0);
}
/**
* Reset the FPGA and activate bootloader
* @mgr a valid FPGA manager device instance
* Return: 0 on success, otherwise a negative errno number
*/
static int svec_fpga_reset(struct fpga_manager *mgr)
{
svec_fpga_loader_unlock(mgr);
if (!svec_fpga_loader_is_active(mgr)) {
dev_err(&mgr->dev, "FPGA loader unavailable\n");
return -ENXIO;
}
return 0;
}
/**
* It is usable only when there is a valid CR/CSR space mapped
......@@ -319,7 +329,7 @@ static int svec_fpga_write_start(struct fpga_manager *mgr)
struct svec_dev *svec = mgr->priv;
struct vme_dev *vdev = to_vme_dev(svec->dev.parent);
void *loader_addr = vdev->map_cr.kernel_va + SVEC_BASE_LOADER;
int err, succ;
int err;
/* reset the FPGA */
err = svec_fpga_reset(mgr);
......@@ -327,13 +337,6 @@ static int svec_fpga_write_start(struct fpga_manager *mgr)
dev_err(&mgr->dev, "FPGA reset failed\n");
goto err_reset;
}
/* check if the FPGA loader is active */
succ = svec_fpga_loader_is_active(mgr);
if (!succ) {
dev_err(&mgr->dev, "FPGA loader unavailable\n");
err = -ENXIO;
goto err_active;
}
/* Reset the Xilinx Passive Serial boot interface */
iowrite32be(XLDR_CSR_SWRST,
......@@ -342,7 +345,6 @@ static int svec_fpga_write_start(struct fpga_manager *mgr)
iowrite32be(XLDR_CSR_START | XLDR_CSR_MSBF,
loader_addr + XLDR_REG_CSR);
err_active:
err_reset:
return err;
}
......
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