The column signals where not properly driven, preventing to light the led independantly.

An address counter is automatically incremented on data r/w.

Add ddr test testbench to repo.

 - Rename SVEC dir into EDA-02530-V0-0_SVEC.
 - Remove SVFC dir.
 - Add VME P2 tester Altium design (P2_tester).

Should be move to general core lib sometime.

sfpga_bootloader: removed unused VME pins from top level entity, referenced general-cores repo as a submodule

hdl/top/sfpga_bootloader: start up in passive mode (requires pullup->pulldown mod on SVEC V0), added IDR register value

hdl: directory structure cleanup (moved template top levels to top/templates), removed unused package dependency from svec_bootloader

added SATA power connector and optional USB connector for stand-alone operation. Added optional UFL clock connector to supply custom FMC cards requiring precise synchronization

--no commit message