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Simple VME FMC Carrier SVEC
Commit 71997739 authored by Greg's avatar Greg
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just backup of 2 days of work

parent a16e1586
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Showing with 122 additions and 60 deletions
circuit_board/SVEC/SVEC.OutJob
View file @ 71997739
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circuit_board/SVEC/SVEC.PrjPcb
View file @ 71997739
......@@ -111,13 +111,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document6]
DocumentPath=Schematics\FMC_CONNECTORS.SchDoc
DocumentPath=Schematics\FPGA_GTP.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=5
AnnotateOrder=6
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -127,13 +127,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document7]
DocumentPath=Schematics\FPGA_GTP.SchDoc
DocumentPath=Schematics\FrontPanel.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=6
AnnotateOrder=7
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -143,13 +143,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document8]
DocumentPath=Schematics\FrontPanel.SchDoc
DocumentPath=Schematics\JTAG Chain + SFPGA Flash.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=7
AnnotateOrder=8
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -159,13 +159,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document9]
DocumentPath=Schematics\JTAG&CONFIG.SchDoc
DocumentPath=PCB-Layout\SVEC.pcbdoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=8
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -191,13 +191,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document11]
DocumentPath=PCB-Layout\SVFC.pcbdoc
DocumentPath=Schematics\SFPGA.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=10
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -207,13 +207,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document12]
DocumentPath=Schematics\SFPGA.SchDoc
DocumentPath=Schematics\SFPGA_power.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=10
AnnotateOrder=11
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -223,13 +223,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document13]
DocumentPath=Schematics\SFPGA_power.SchDoc
DocumentPath=Schematics\USB_interface.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=11
AnnotateOrder=13
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -239,13 +239,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document14]
DocumentPath=Schematics\USB.SchDoc
DocumentPath=Schematics\SVEC_TOP.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=13
AnnotateOrder=12
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -255,13 +255,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document15]
DocumentPath=Schematics\SVEC_TOP.SchDoc
DocumentPath=Schematics\VMEConnectors.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=12
AnnotateOrder=14
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -271,13 +271,13 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document16]
DocumentPath=Schematics\VMEConnectors.SchDoc
DocumentPath=SVEC.OutJob
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=14
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -287,7 +287,23 @@ DItemRevisionGUID=
GenerateClassCluster=0
[Document17]
DocumentPath=SVEC.OutJob
DocumentPath=Schematics\FMC_connectors.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=16
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0
[Document18]
DocumentPath=Schematics\PowerSupplies.Txt
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
......@@ -303,10 +319,26 @@ DItemRevisionGUID=
GenerateClassCluster=0
[GeneratedDocument1]
DocumentPath=Project Outputs for SVEC\Design Rule Check - SVFC.html
DocumentPath=Project Outputs for SVEC\Design Rule Check - SVEC.html
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for SVEC\Design Rule Check - SVFC.html
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=Project Outputs for SVEC\Move Component(s) Origin To Grid - SVEC.html
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for SVEC\Reports\PowerSupplies.BOM
DItemRevisionGUID=
[GeneratedDocument5]
DocumentPath=Project Outputs for SVEC\Reports\PowerSupplies.CSV
DItemRevisionGUID=
[GeneratedDocument6]
DocumentPath=PCB-Layout\SVFC.pcbdoc.htm
DItemRevisionGUID=
......@@ -833,53 +865,53 @@ Name=Report Outputs
Description=
TargetPrinter=OKI B4100 (MS)
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=SimpleBOM
OutputName1=Simple BOM
OutputType1=ComponentCrossReference
OutputName1=Component Cross Reference Report
OutputDocumentPath1=
OutputVariantName1=[No Variations]
OutputDefault1=0
Configuration1_Name1=OutputConfigurationParameter1
Configuration1_Item1=Record=SimpleBOMView|SimpleBOMMode=0
OutputType2=BOM_PartType
OutputName2=Bill of Materials
OutputType2=Script
OutputName2=Script Output
OutputDocumentPath2=
OutputVariantName2=[No Variations]
OutputDefault2=0
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
Configuration2_Name1=Filter
Configuration2_Item1=545046300E5446696C74657257726170706572000D46696C7465722E416374697665090F46696C7465722E43726974657269610A04000000000000000000
Configuration2_Name2=General
Configuration2_Item2=OpenExported=False|AddToProject=False|ForceFit=True|NotFitted=False|Database=False|IncludePCBData=False|ShowExportOptions=True|TemplateFilename=..\..\..\Altium\CERN_Files\Templates\BOM\CERN-AltiumMat Template.XLT|BatchMode=5|FormWidth=1343|FormHeight=796|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=<none>
Configuration2_Name3=GroupOrder
Configuration2_Item3=Part Number=True
Configuration2_Name4=PCBDocument
Configuration2_Item4=
Configuration2_Name5=SortOrder
Configuration2_Item5=Designator=Up
Configuration2_Name6=VisibleOrder
Configuration2_Item6=Part Number=241|Designator=97|Quantity=62|Part Description=241|Comment=87|Manufacturer=162|Case=127|Manufacturer Part Number=168|Footprint=100|Mounted=100
OutputType3=ReportHierarchy
OutputName3=Report Project Hierarchy
OutputType3=SinglePinNetReporter
OutputName3=Report Single Pin Nets
OutputDocumentPath3=
OutputVariantName3=[No Variations]
OutputDefault3=0
Configuration3_Name1=OutputConfigurationParameter1
Configuration3_Item1=Record=ReportHierarchyView|ReportHierarchyMode=0
OutputType4=ComponentCrossReference
OutputName4=Component Cross Reference Report
OutputType4=SimpleBOM
OutputName4=Simple BOM
OutputDocumentPath4=
OutputVariantName4=[No Variations]
OutputDefault4=0
OutputType5=Script
OutputName5=Script Output
Configuration4_Name1=OutputConfigurationParameter1
Configuration4_Item1=Record=SimpleBOMView|SimpleBOMMode=0
OutputType5=BOM_PartType
OutputName5=Bill of Materials
OutputDocumentPath5=
OutputVariantName5=[No Variations]
OutputDefault5=0
OutputType6=SinglePinNetReporter
OutputName6=Report Single Pin Nets
PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
Configuration5_Name1=Filter
Configuration5_Item1=545046300E5446696C74657257726170706572000D46696C7465722E416374697665090F46696C7465722E43726974657269610A04000000000000000000
Configuration5_Name2=General
Configuration5_Item2=OpenExported=False|AddToProject=False|ForceFit=True|NotFitted=False|Database=False|IncludePCBData=False|ShowExportOptions=True|TemplateFilename=..\..\..\Altium\CERN_Files\Templates\BOM\CERN-AltiumMat Template.XLT|BatchMode=5|FormWidth=1343|FormHeight=796|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=<none>
Configuration5_Name3=GroupOrder
Configuration5_Item3=Part Number=True
Configuration5_Name4=PCBDocument
Configuration5_Item4=
Configuration5_Name5=SortOrder
Configuration5_Item5=Designator=Up
Configuration5_Name6=VisibleOrder
Configuration5_Item6=Part Number=241|Designator=97|Quantity=62|Part Description=241|Comment=87|Manufacturer=162|Case=127|Manufacturer Part Number=168|Footprint=100|Mounted=100
OutputType6=ReportHierarchy
OutputName6=Report Project Hierarchy
OutputDocumentPath6=
OutputVariantName6=[No Variations]
OutputDefault6=0
Configuration6_Name1=OutputConfigurationParameter1
Configuration6_Item1=Record=ReportHierarchyView|ReportHierarchyMode=0
[OutputGroup7]
Name=Other Outputs
......
circuit_board/SVEC/SVEC.PrjPcbStructure
View file @ 71997739
......@@ -6,12 +6,12 @@ Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_2|SchDesigna
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FMC_CONNECTORS.SchDoc|SymbolType=Normal|RawFileName=FMC_CONNECTORS.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=fpga_gtp.SchDoc|SymbolType=Normal|RawFileName=fpga_gtp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FrontPanel|SchDesignator=U_FrontPanel|FileName=FrontPanel.SchDoc|SymbolType=Normal|RawFileName=FrontPanel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_JTAG&CONFIG|SchDesignator=U_JTAG&CONFIG|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_JTAG Chain + SFPGA Flash|SchDesignator=U_JTAG Chain + SFPGA Flash|FileName=JTAG Chain + SFPGA Flash.SchDoc|SymbolType=Normal|RawFileName=JTAG Chain + SFPGA Flash.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=PowerSupplies.SchDoc|SymbolType=Normal|RawFileName=PowerSupplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB.SchDoc|SymbolType=Normal|RawFileName=USB.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB_interface.SchDoc|SymbolType=Normal|RawFileName=USB_interface.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VmeConnectors.SchDoc|SymbolType=Normal|RawFileName=VmeConnectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=SVEC_TOP.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC19|DocumentName=AFPGA.SchDoc|LibraryReference=XC6SLX150T-2FGG900C|SubProjectPath= |Configuration= |Description=SPARTAN-6, FPGA, 900-Ball BGA, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX150T-2FGG900C|SubPartUniqueId1=NGIDIYWR|SubPartDocPath1=AFPGA.SchDoc|SubPartUniqueId2=FUNNCDPN|SubPartDocPath2=AFPGA.SchDoc|SubPartUniqueId3=QBXJFLEN|SubPartDocPath3=AFPGA.SchDoc|SubPartUniqueId4=JJOQTPQG|SubPartDocPath4=AFPGA.SchDoc|SubPartUniqueId5=DUYJDUAV|SubPartDocPath5=AFPGA.SchDoc|SubPartUniqueId6=MEKFUFMR|SubPartDocPath6=AFPGA.SchDoc|SubPartUniqueId7=EWTIHSSR|SubPartDocPath7=AFPGA.SchDoc|SubPartUniqueId8=VYVXECCI|SubPartDocPath8=DDR3.SchDoc|SubPartUniqueId9=HGYTKHSM|SubPartDocPath9=DDR3_2.SchDoc|SubPartUniqueId10=HVOTMCXP|SubPartDocPath10=FPGA_GTP.SchDoc|SubPartUniqueId11=DJFABCDT|SubPartDocPath11=FPGA_GTP.SchDoc|SubPartUniqueId12=SUEJCWVA|SubPartDocPath12=FPGA_GTP.SchDoc|SubPartUniqueId13=IJQHRHAL|SubPartDocPath13=FPGA_GTP.SchDoc|SubPartUniqueId14=RIFFUJKX|SubPartDocPath14=JTAG&CONFIG.SchDoc|SubPartUniqueId15=TNOTCNVT|SubPartDocPath15=AFPGA_power.SchDoc|SubPartUniqueId16=VINGWMCL|SubPartDocPath16=AFPGA_power.SchDoc|SubPartUniqueId17=KPAAVKWI|SubPartDocPath17=AFPGA_power.SchDoc|SubPartUniqueId18=TWWKQKGX|SubPartDocPath18=AFPGA_power.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=QTOJQSMD|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=AOYRMHFT|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=OLSNOCAD|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=LFMNKHSD|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG&CONFIG.SchDoc|SubPartUniqueId6=WVUDHYEK|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=FATYVDMF|SubPartDocPath7=SFPGA_power.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC19|DocumentName=AFPGA.SchDoc|LibraryReference=XC6SLX150T-2FGG900C|SubProjectPath= |Configuration= |Description=SPARTAN-6, FPGA, 900-Ball BGA, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX150T-2FGG900C|SubPartUniqueId1=NGIDIYWR|SubPartDocPath1=AFPGA.SchDoc|SubPartUniqueId2=FUNNCDPN|SubPartDocPath2=AFPGA.SchDoc|SubPartUniqueId3=QBXJFLEN|SubPartDocPath3=AFPGA.SchDoc|SubPartUniqueId4=JJOQTPQG|SubPartDocPath4=AFPGA.SchDoc|SubPartUniqueId5=DUYJDUAV|SubPartDocPath5=AFPGA.SchDoc|SubPartUniqueId6=MEKFUFMR|SubPartDocPath6=AFPGA.SchDoc|SubPartUniqueId7=EWTIHSSR|SubPartDocPath7=AFPGA.SchDoc|SubPartUniqueId8=VYVXECCI|SubPartDocPath8=DDR3.SchDoc|SubPartUniqueId9=HGYTKHSM|SubPartDocPath9=DDR3_2.SchDoc|SubPartUniqueId10=HVOTMCXP|SubPartDocPath10=FPGA_GTP.SchDoc|SubPartUniqueId11=DJFABCDT|SubPartDocPath11=FPGA_GTP.SchDoc|SubPartUniqueId12=SUEJCWVA|SubPartDocPath12=FPGA_GTP.SchDoc|SubPartUniqueId13=IJQHRHAL|SubPartDocPath13=FPGA_GTP.SchDoc|SubPartUniqueId14=RIFFUJKX|SubPartDocPath14=JTAG Chain + SFPGA Flash.SchDoc|SubPartUniqueId15=TNOTCNVT|SubPartDocPath15=AFPGA_power.SchDoc|SubPartUniqueId16=VINGWMCL|SubPartDocPath16=AFPGA_power.SchDoc|SubPartUniqueId17=KPAAVKWI|SubPartDocPath17=AFPGA_power.SchDoc|SubPartUniqueId18=TWWKQKGX|SubPartDocPath18=AFPGA_power.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=QTOJQSMD|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=AOYRMHFT|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=OLSNOCAD|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=LFMNKHSD|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG Chain + SFPGA Flash.SchDoc|SubPartUniqueId6=WVUDHYEK|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=FATYVDMF|SubPartDocPath7=SFPGA_power.SchDoc
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