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Simple VME FMC Carrier SVEC
Commit 2d701452 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top/golden: golden bitstream, initial commit, untested

parent b8ddc8a2
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hdl/top/golden/Manifest.py 0 → 100644
View file @ 2d701452
files = [ "svec_top.vhd", "svec_top.ucf", "xvme64x_core.vhd" ]
fetchto = "../../ip_cores"
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ],
"svn" : [ "http://svn.ohwr.org/vme64x-core/trunk/hdl/vme64x-core/rtl" ]
}
hdl/top/golden/svec_top.ucf 0 → 100644
View file @ 2d701452
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y7;
NET "vme_ds_n_i[0]" LOC = Y6;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[6]" LOC = R7;
NET "vme_irq_n_o[5]" LOC = AH2;
NET "vme_irq_n_o[4]" LOC = AF2;
NET "vme_irq_n_o[3]" LOC = N9;
NET "vme_irq_n_o[2]" LOC = N10;
NET "vme_irq_n_o[1]" LOC = AH4;
NET "vme_irq_n_o[0]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" LOC = V26;
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "tempid_dq_b" LOC = AC30;
#===============================================================================
# IO Standard Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33";
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[0]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
NET "tempid_dq_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_prsntm2c_n_i" LOC = N30;
NET "fmc0_scl_b" LOC = P28;
NET "fmc0_sda_b" LOC = P30;
NET "fmc1_prsntm2c_n_i" LOC = AE29;
NET "fmc1_scl_b" LOC = W29;
NET "fmc1_sda_b" LOC = V30;
NET "fmc0_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc1_sda_b" IOSTANDARD = "LVCMOS33";
hdl/top/golden/svec_top.vhd 0 → 100644
View file @ 2d701452
This diff is collapsed.
hdl/top/golden/xvme64x_core.vhd 0 → 100644
View file @ 2d701452
library ieee;
use ieee.STD_LOGIC_1164.all;
use WORK.wishbone_pkg.all;
entity xvme64x_core is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic
);
end xvme64x_core;
architecture wrapper of xvme64x_core is
component VME64xCore_Top
generic(
g_width : integer := 32;
g_addr_width : integer := 64;
g_CRAM_SIZE : integer := 1024
);
port (
clk_i : in std_logic;
reset_o : out std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(g_width / 8 - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
INT_ack : out std_logic;
IRQ_i : in std_logic;
leds : out std_logic_vector(7 downto 0));
end component;
signal rst_in, rst_out : std_logic;
signal dat_out, dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(63 downto 0);
begin -- wrapper
rst_in <= not rst_n_i;
rst_n_o <= rst_n_i and (not rst_out);
U_Wrapped_VME : VME64xCore_Top
port map (
clk_i => clk_i,
reset_o => rst_out,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b_i => VME_LWORD_n_b_i,
VME_LWORD_n_b_o => VME_LWORD_n_b_o,
VME_ADDR_b_i => VME_ADDR_b_i,
VME_ADDR_b_o => VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b_i,
VME_DATA_b_o => VME_DATA_b_o,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
DAT_i => dat_in,
DAT_o => dat_out,
ADR_o => adr_out,
CYC_o => master_o.cyc,
ERR_i => master_i.err,
RTY_i => master_i.rty,
SEL_o => open,
STB_o => master_o.stb,
ACK_i => master_i.ack,
WE_o => master_o.we,
STALL_i => master_i.stall,
IRQ_i => irq_i,
INT_ack => irq_ack_o);
master_o.dat <= dat_out(31 downto 0);
master_o.sel <= (others => '1');
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
end wrapper;
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