Skip to content

S
Simple VME FMC Carrier SVEC
Commit 4728f2bd authored by Greg's avatar Greg
Browse files
Options

added SATA power connector and optional USB connector for stand-alone operation.… 

added SATA power connector and optional USB connector for stand-alone operation. Added optional UFL clock connector to supply custom FMC cards requiring precise synchronization
parent 25de20e0
Hide whitespace changes
Inline Side-by-side
Showing with 19 additions and 27 deletions
circuit_board/SVEC/SVEC.PrjPcb
View file @ 4728f2bd
......@@ -261,7 +261,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=20
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -277,7 +277,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=18
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -293,7 +293,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=19
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -309,7 +309,7 @@ AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
AnnotateOrder=17
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
......@@ -322,14 +322,6 @@ GenerateClassCluster=0
DocumentPath=Project Outputs for SVEC\Design Rule Check - SVEC.html
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for SVEC\Reports\SVEC.BOM
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=Project Outputs for SVEC\Reports\SVEC.CSV
DItemRevisionGUID=
[PCBConfiguration1]
ReleaseItemId=
CurrentRevision=
......
circuit_board/SVEC/SVEC.PrjPcbStructure
View file @ 4728f2bd
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_AFPGA|SchDesignator=U_AFPGA|FileName=AFPGA.SchDoc|SymbolType=Normal|RawFileName=AFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=Clk_generation.SchDoc|SymbolType=Normal|RawFileName=Clk_generation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_DDR3_1|SchDesignator=U_DDR3_1|FileName=DDR3.SchDoc|SymbolType=Normal|RawFileName=DDR3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_DDR3_2|SchDesignator=U_DDR3_2|FileName=DDR3_2.SchDoc|SymbolType=Normal|RawFileName=DDR3_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FMC_connectors.SchDoc|SymbolType=Normal|RawFileName=FMC_connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=FPGA_GTP.SchDoc|SymbolType=Normal|RawFileName=FPGA_GTP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_FrontPanel|SchDesignator=U_FrontPanel|FileName=Front_panel.SchDoc|SymbolType=Normal|RawFileName=Front_panel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_JTAG Chain + SFPGA Flash|SchDesignator=U_JTAG Chain + SFPGA Flash|FileName=JTAG Chain + SFPGA Flash.SchDoc|SymbolType=Normal|RawFileName=JTAG Chain + SFPGA Flash.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=Power_supplies.SchDoc|SymbolType=Normal|RawFileName=Power_supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB_interface.SchDoc|SymbolType=Normal|RawFileName=USB_interface.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_top.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VME_connectors.SchDoc|SymbolType=Normal|RawFileName=VME_connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=SVEC_top.SchDoc
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA|SchDesignator=U_AFPGA|FileName=AFPGA.SchDoc|SymbolType=Normal|RawFileName=AFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_AFPGA_power|SchDesignator=U_AFPGA_power|FileName=AFPGA_power.SchDoc|SymbolType=Normal|RawFileName=AFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_ClkGeneration|SchDesignator=U_ClkGeneration|FileName=Clk_generation.SchDoc|SymbolType=Normal|RawFileName=Clk_generation.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_1|SchDesignator=U_DDR3_1|FileName=DDR3.SchDoc|SymbolType=Normal|RawFileName=DDR3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_DDR3_2|SchDesignator=U_DDR3_2|FileName=DDR3_2.SchDoc|SymbolType=Normal|RawFileName=DDR3_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FmcConnectors|SchDesignator=U_FmcConnectors|FileName=FMC_connectors.SchDoc|SymbolType=Normal|RawFileName=FMC_connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=FPGA_GTP.SchDoc|SymbolType=Normal|RawFileName=FPGA_GTP.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_FrontPanel|SchDesignator=U_FrontPanel|FileName=Front_panel.SchDoc|SymbolType=Normal|RawFileName=Front_panel.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_JTAG Chain + SFPGA Flash|SchDesignator=U_JTAG Chain + SFPGA Flash|FileName=JTAG Chain + SFPGA Flash.SchDoc|SymbolType=Normal|RawFileName=JTAG Chain + SFPGA Flash.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_PowerSupplies|SchDesignator=U_PowerSupplies|FileName=Power_supplies.SchDoc|SymbolType=Normal|RawFileName=Power_supplies.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA|SchDesignator=U_SFPGA|FileName=SFPGA.SchDoc|SymbolType=Normal|RawFileName=SFPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_SFPGA_power|SchDesignator=U_SFPGA_power|FileName=SFPGA_power.SchDoc|SymbolType=Normal|RawFileName=SFPGA_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_USB|SchDesignator=U_USB|FileName=USB_interface.SchDoc|SymbolType=Normal|RawFileName=USB_interface.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=SVEC_TOP.SchDoc|Designator=U_VmeConnectors|SchDesignator=U_VmeConnectors|FileName=VME_connectors.SchDoc|SymbolType=Normal|RawFileName=VME_connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=TopLevelDocument|FileName=SVEC_TOP.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC19|DocumentName=AFPGA.SchDoc|LibraryReference=XC6SLX150T-2FGG900C|SubProjectPath= |Configuration= |Description=SPARTAN-6, FPGA, 900-Ball BGA, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX150T-2FGG900C|SubPartUniqueId1=NGIDIYWR|SubPartDocPath1=AFPGA.SchDoc|SubPartUniqueId2=FUNNCDPN|SubPartDocPath2=AFPGA.SchDoc|SubPartUniqueId3=QBXJFLEN|SubPartDocPath3=AFPGA.SchDoc|SubPartUniqueId4=JJOQTPQG|SubPartDocPath4=AFPGA.SchDoc|SubPartUniqueId5=DUYJDUAV|SubPartDocPath5=AFPGA.SchDoc|SubPartUniqueId6=MEKFUFMR|SubPartDocPath6=AFPGA.SchDoc|SubPartUniqueId7=EWTIHSSR|SubPartDocPath7=AFPGA.SchDoc|SubPartUniqueId8=VYVXECCI|SubPartDocPath8=DDR3.SchDoc|SubPartUniqueId9=HGYTKHSM|SubPartDocPath9=DDR3_2.SchDoc|SubPartUniqueId10=HVOTMCXP|SubPartDocPath10=FPGA_GTP.SchDoc|SubPartUniqueId11=DJFABCDT|SubPartDocPath11=FPGA_GTP.SchDoc|SubPartUniqueId12=SUEJCWVA|SubPartDocPath12=FPGA_GTP.SchDoc|SubPartUniqueId13=IJQHRHAL|SubPartDocPath13=FPGA_GTP.SchDoc|SubPartUniqueId14=RIFFUJKX|SubPartDocPath14=JTAG Chain + SFPGA Flash.SchDoc|SubPartUniqueId15=TNOTCNVT|SubPartDocPath15=AFPGA_power.SchDoc|SubPartUniqueId16=VINGWMCL|SubPartDocPath16=AFPGA_power.SchDoc|SubPartUniqueId17=KPAAVKWI|SubPartDocPath17=AFPGA_power.SchDoc|SubPartUniqueId18=TWWKQKGX|SubPartDocPath18=AFPGA_power.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC40|DocumentName=SFPGA.SchDoc|LibraryReference=XC6SLX9-2FTG256C|SubProjectPath= |Configuration= |Description=Spartan-6 LX 1.2V FPGA, 186 User I/Os, 256-Ball Fine-Pitch Thin BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free|NexusDeviceId=XC6SLX9-2FTG256C|SubPartUniqueId1=QTOJQSMD|SubPartDocPath1=SFPGA.SchDoc|SubPartUniqueId2=AOYRMHFT|SubPartDocPath2=SFPGA.SchDoc|SubPartUniqueId3=OLSNOCAD|SubPartDocPath3=SFPGA.SchDoc|SubPartUniqueId4=LFMNKHSD|SubPartDocPath4=SFPGA.SchDoc|SubPartUniqueId5=ODYKENES|SubPartDocPath5=JTAG Chain + SFPGA Flash.SchDoc|SubPartUniqueId6=WVUDHYEK|SubPartDocPath6=SFPGA_power.SchDoc|SubPartUniqueId7=FATYVDMF|SubPartDocPath7=SFPGA_power.SchDoc
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment