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Page version Author Changes Last updated
d80f374d Peter Jansweijer
Cleaned Main Features section (old status still available under Design specification August 2019 link)
850152a4 Peter Jansweijer
added link to Design Specification (status August 2019)
4ceeae7d Erik van der Bij
Added Planning in Status table
52e1c61d Peter Jansweijer
Update Home
c41fe4fd Peter Jansweijer
Link schematics (Abracon_Powered_190814)
5249432e Peter Jansweijer
Update Home
135d2f46 Peter Jansweijer
replaced SPEC picture with SPEC7 status dated 190716
c92e0b67 Peter Jansweijer
other reference clock
5c9725e8 Peter Jansweijer
clearify Bulls-Eye signals (Z030/Z035)
4ee5b8a3 Erik van der Bij
14-layer PCB
a2dcbee7 Peter Jansweijer
added link to preliminairy schematics
dbdd84ed Erik van der Bij
Removed double references to SVEC and SPEXI in intro.
0aaf6494 Erik van der Bij
Status: Schematics updated after schematics review. Layout can start.
3cf7650c Erik van der Bij
Named URL "Zynq-7000 SoC Technical Reference Manual"
ae2e7087 Peter Jansweijer
repaired indentation
44cc0c30 Peter Jansweijer
Update Home
16e26a61 Erik van der Bij
Put <br/> in status table entries to make dates fit on single line
a70a7cef Erik van der Bij
Mention Zynq in intro. Pbl present in layout from Clocking resources on
485250c4 Peter Jansweijer
refined last updated specifications after schematics review.
6cbfa3f8 Peter Jansweijer
Updated specifications after schematics review.