| ... | ... | @@ -57,12 +57,10 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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[manual](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf#page=91/.)*
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- 2.5V can only be used with a LPC FMC mezzanine: only the LPC
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pins (LA bank) are 2.5V tolerant.</s>
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- <s>Limited, partial connectivity of HPC part, 1.8V tolerant only
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- **xx** signals on HA bank
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- HA bank only 1.8V tolerant (Vadj set to 1.8V)
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- only when Xilinx Z035 or Z045 is mounted, the DP1\_M2C/C2M
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and DP2\_M2C/2CM are connected to two GTX transceivers </s>
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- <s>Limited, partial connectivity of HPC part, 1.8V tolerant only</s>
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- <s>**xx** signals on HA bank</s>
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- <s>HA bank only 1.8V tolerant (Vadj set to 1.8V)</s>
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- <s>only when Xilinx Z035 or Z045 is mounted, the DP1\_M2C/C2M and DP2\_M2C/2CM are connected to two GTX transceivers </s>
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- Clocking resources
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- 1x Fixed frequency **33.33 MHz** oscillator for Application processor unit
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(APU),<s> (frequency?)</s>
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