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@@ -4,12 +4,9 @@
 
 **The FMC PCIe Carrier called SPEC7 is an FMC carrier that can hold one
 FMC card and an SFP connector.**  
-This board is optimised for low jitter and cost and is usable with most
-of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
+This board uses a Xilinx Zynq FPGA with Dual-Core ARM processor integrated and is optimised for low jitter and cost and is usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
 Delay).  
-The design is done in a collaboration between
-[NIKHEF](https://www.nikhef.nl/en/) (NL) and CERN as both need a card
-with a similar functionality.
+The design is done in a collaboration between [NIKHEF](https://www.nikhef.nl/en/) (NL) and CERN as both need a card with a similar functionality.
 
 The SPEC7 is the follow-up of the
 [SPEC](https://www.ohwr.org/project/spec/wiki) of which the design
@@ -33,8 +30,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
   - 2-lane PCIe Gen2
       - Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge
         integrated in FPGA
-  - Xilinx Zynq FPGA with Dual-Core ARM processor
-        integrated
+  - Xilinx Zynq FPGA with Dual-Core ARM processor integrated
       - [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
         (-1= slowest, commercial temp range, fast enough for most
         applications) 
@@ -66,6 +62,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)**
           - HA bank only 1.8V tolerant (Vadj set to 1.8V)
           - only when Xilinx Z035 or Z045 is mounted, the DP1\_M2C/C2M
             and DP2\_M2C/2CM are connected to two GTX transceivers </s>
+
   - Clocking resources
       - 1x Fixed frequency **33.33 MHz** oscillator for Application processor unit
         (APU),<s> (frequency?)</s>