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**The FMC PCIe Carrier called SPEC7 is an FMC carrier that can hold one
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FMC card and an SFP connector.**
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This board is optimised for low jitter and cost and is usable with most
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of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
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This board uses a Xilinx Zynq FPGA with Dual-Core ARM processor integrated and is optimised for low jitter and cost and is usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine
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Delay).
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The design is done in a collaboration between
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[NIKHEF](https://www.nikhef.nl/en/) (NL) and CERN as both need a card
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with a similar functionality.
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The design is done in a collaboration between [NIKHEF](https://www.nikhef.nl/en/) (NL) and CERN as both need a card with a similar functionality.
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The SPEC7 is the follow-up of the
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[SPEC](https://www.ohwr.org/project/spec/wiki) of which the design
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... | ... | @@ -33,8 +30,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- 2-lane PCIe Gen2
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- Same 1 GByte/s total speed as 4-lane PCIe Gen1 on SPEC. Bridge
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integrated in FPGA
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- Xilinx Zynq FPGA with Dual-Core ARM processor
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integrated
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- Xilinx Zynq FPGA with Dual-Core ARM processor integrated
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- [XC7Z030-1FBG676C](https://www.xilinx.com/support/documentation/selection-guides/zynq-7000-product-selection-guide.pdf)
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(-1= slowest, commercial temp range, fast enough for most
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applications)
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... | ... | @@ -66,6 +62,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- HA bank only 1.8V tolerant (Vadj set to 1.8V)
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- only when Xilinx Z035 or Z045 is mounted, the DP1\_M2C/C2M
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and DP2\_M2C/2CM are connected to two GTX transceivers </s>
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- Clocking resources
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- 1x Fixed frequency **33.33 MHz** oscillator for Application processor unit
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(APU),<s> (frequency?)</s>
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