| ... | ... | @@ -52,11 +52,9 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- <s>Under discussion. Possibly only GTX lines connected and Vadj
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fixed at 2.5V (23/10/18)</s>
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- **Vadj fixed 2.5V (HR bank of the ZYNQ only allows LVDS_25 at VCCO 2V5, see UG471 table 1-43)**
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-<s> *1.8V not possible due to LVDS level restrictions on the
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7-series HR-IO banks, as can be read on page 91 of the
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[manual](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf#page=91/.)*
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- 2.5V can only be used with a LPC FMC mezzanine: only the LPC
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pins (LA bank) are 2.5V tolerant.</s>
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-<s>*1.8V not possible due to LVDS level restrictions on the 7-series HR-IO banks, as can be read on page 91 of the
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[manual](https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf#page=91/.)*</s>
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- <s>2.5V can only be used with a LPC FMC mezzanine: only the LPC pins (LA bank) are 2.5V tolerant.</s>
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- <s>Limited, partial connectivity of HPC part, 1.8V tolerant only</s>
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- <s>**xx** signals on HA bank</s>
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- <s>HA bank only 1.8V tolerant (Vadj set to 1.8V)</s>
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| ... | ... | @@ -113,6 +111,7 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- One to UART interface of the ARM
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- One to user logic (e.g., PTP core)
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- 1x <s>USB-C</s> **USB Type A** connector connected to USB **2.0** port of the ARM
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- Ethernet RJ45 connector + magnetics and **MicroChip KSZ9031RNX, 10/100/1000 Mbps** PHY (interface to ARM GigE)
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- Samtec Bulls-Eye connector ([BDRA: 20 signals on the PCB](https://www.samtec.com/products/bdra), **1.3 x 5.0 = 6.5 cm2** land pattern, user mountable connector) **or** ([BARA: 22 signals on the PCB](https://www.samtec.com/products/bara), **1.8 x 2.1 = 4 cm2 land pattern, user mountable connector); BDRA probably better supported but slightly bigger, final choise BDRA/BARA will depend on PCB layout**
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- ESD protection on all signals
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- **10 differential signals:**
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| ... | ... | @@ -122,7 +121,6 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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- **PPS in/out**
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- **1x GTX Tx/Rx**
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- **1x spare**
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- Ethernet RJ45 connector + magnetics and **MicroChip KSZ9031RNX, 10/100/1000 Mbps** PHY (interface to ARM GigE)
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- 1x connector for optional cooling fan
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- FPGA configuration. The FPGA can optionally be programmed from:
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- JTAG header
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| ... | ... | @@ -213,5 +211,5 @@ board*](https://www.ohwr.org/project/spec/wiki) (shown)** |
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-----
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29 March 2019
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1 April 2019
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