The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
SFP connector. On the PCIe side it has a 4-lane interface, while the FMC
mezzanine slot uses a low-pin count connector. This board is optimised
for cost and will be usable with most of the FMC cards designed within
the OHR project (e.g. ADC cards, Fine Delay). For boards needing more
possibilities (e.g. programmable clock resources, fast SRAM, fast
interconnect between carriers), the FMC PCIe
Carrier or its VME
counter part can be used.
Other FMC projects and the FMC standard are described in FMC
SPEC_under_design.bmp Image of PCB under design.*
* 4-lane PCIe (Gennum GN4124)
* FMC slot with low pin count (LPC) connector
o Vadj fixed to 2.5V
o No dedicated clock signals from Carrier to FMC (only available on HPC
o LPC cheaper than HPC and also easier to mount
o FMC connectivity: all 34 differential pairs connected, 1 GTP
transceiver with clock, 2 clock pairs, JTAG
* 1 Spartan6 FPGA (XC6SLX45T)
* Simple clocking resources
o 1 10-280 MHz Programmable XO Oscillator (Silicon Labs Si570)
o 2 25 MHz TCXOs controlled by a DAC
o 1 low-jitter frequency synthesizer (TI CDCM61004)
* On board memory
o A 2Gbit DDR3
o 1 SPI 128Mbit flash PROM for multiboot FPGA powerup configuration,
storage of the FPGA firmware or of critical data
* Front panel containing
o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver
o Programmable LED
o FMC front panel
* Internal connectors
o 1 JTAG header for Xilinx programming during debugging
o 1 or 2 SATA connectors if don't add much cost
* FPGA configuration. The FPGA can optionally be programmed from:
o GN4124 SPRIO interface (loaded by software driver at startup)
o JTAG header
o SPI 128Mbit flash PROM
o selectable by assembly of 0 Ohm resistors. Default option would be
loading via the GN4124 at driver startup.
* Optimised for cost
Detailed project information
Start of project. Design will be done by an external company, based on the FMC PCIe Carrier. Reviewing will be done by CERN.
Main features reviewed by JS, PA, MC & EB. Design can start.
First schematics published. Ready for review.
First review held. Considered as a preliminary review as schematics not finished.
Second version schematics published.
Second schematics review held. FMC to Xilinx bank connections not correct. Clock missing. Supply Xilinx wrong. Cleanup required.
Schematics corrected. Waiting for a final schematics review from CERN.