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Hdlmake
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Ugly report messages if synthesis tool not found
#48
· opened
Feb 07, 2015
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Vivado doesn't support SPEC V4 counter test
#47
· opened
Feb 07, 2015
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
VHDL: attributes
#46
· opened
Mar 27, 2015
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
Have only one call to os.getcwd()
#45
· opened
Oct 13, 2015
by
Nicolas Chevillot
feature
CLOSED
2
updated
Feb 12, 2019
Hdlmake v2.1 not cleaning fetched modules
#44
· opened
Jan 19, 2016
by
Marco Roda
CLOSED
1
updated
Feb 12, 2019
Cannot list files from outside a top module
#42
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
0
updated
Feb 12, 2019
Wrong version for ISE project in generated .xise files
#41
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Add improved granularity to ISE synthesis makefile
#40
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
feature
CLOSED
0
updated
Feb 12, 2019
Hdlmake now depends on the networkx package
#39
· opened
Mar 30, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
[PATCH] add support for 'cyclone iv e' family
#38
· opened
Mar 30, 2016
by
Javier D. Garcia-Lasheras
support
CLOSED
1
updated
Feb 12, 2019
[PATCH] add support for vhdl libraries in generated quartus .qsf file
#37
· opened
Mar 30, 2016
by
Javier D. Garcia-Lasheras
support
CLOSED
1
updated
Feb 12, 2019
[PATCH] add support for .qsf files (so that modules can contain e.g. pin assignments)
#36
· opened
Mar 30, 2016
by
Javier D. Garcia-Lasheras
support
CLOSED
1
updated
Feb 12, 2019
Add legacy support for Altera tools
#33
· opened
Apr 14, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Relations missing for VHDL package to be used in system verilog
#20
· opened
Jun 01, 2016
by
Nicolas Chevillot
bug
6
updated
Feb 12, 2019
Flatten option for Fetch doesn't work
#16
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Do not fetch submodules recursively
#15
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
multitline signal declaration generates wrong relations in VHDL
#13
· opened
Nov 14, 2016
by
Nicolas Chevillot
bug
0
updated
Feb 12, 2019
VHDL parser: split entity and architecture
#3
· opened
Mar 21, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
VHDL parser: instantiations with archietecture selection
#2
· opened
Mar 21, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
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