Signed-off-by: jozsef imrek <jozsef.imrek@cern.ch>
---
hdlmake/srcfile.py | 6 ++++++
hdlmake/tools/quartus/quartus.py | 4 +++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hdlmake/srcfile.py b/hdlmake/srcfile.py
index d8a25ed..e4246e6 100644
--- a/hdlmake/srcfile.py
+++ b/hdlmake/srcfile.py
@@ -163,6 +163,10 @@ class PDCFile(File):
class WBGenFile(File):
pass
+class QSFFile(File):
+ # Quartus Settings File
+ pass
+
class SourceFileSet(set):
def __init__(self):
@@ -276,4 +280,6 @@ class SourceFileFactory:
nf = EDFFile(path=path, module=module)
elif extension == 'pdc':
nf = PDCFile(path=path, module=module)
+ elif extension == 'qsf':
+ nf = QSFFile(path=path, module=module)
return nf
diff --git a/hdlmake/tools/quartus/quartus.py b/hdlmake/tools/quartus/quartus.py
index 514bc1b..f9b06c1 100644
--- a/hdlmake/tools/quartus/quartus.py
+++ b/hdlmake/tools/quartus/quartus.py
@@ -183,7 +183,7 @@ mrproper:
return pre+'\n'+mod+'\n'+post+'\n'
def __emit_files(self):
- from srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, QIPFile, DPFFile
+ from srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, QIPFile, DPFFile, QSFFile
tmp = "set_global_assignment -name {0} {1}"
tmplib = tmp + " -library {2}"
ret = []
@@ -200,6 +200,8 @@ mrproper:
line = tmp.format("QIP_FILE", f.rel_path())
elif isinstance(f, DPFFile):
line = tmp.format("MISC_FILE", f.rel_path())
+ elif isinstance(f, QSFFile):
+ line = tmp.format("SOURCE_TCL_SCRIPT_FILE", f.rel_path())
else:
continue
ret.append(line)
--
1.8.3.1