read throughput improvement (issue next read when there is space instead of waiting for output fifo to be empty)
add generic to insert AXI_Pipeline stages in-front of specific gencores fifos for timing.

testbench is parameterised to simplify testing with / without AXI and WB_DMA
update style on most files

make TID/CID a generic and check the CID value on receipt

Restructure testbench so testcases are atomic and self-checking (where possible)
some more testbench infra tasks
unused testcase for 4KB PCIE MASTER write - possible 4KB boundary bug (SW maskable)

Also fix some typos.

Remove unused signals, renaming.

And refactoring.

3.0.1 - 2020-09-29
==================
https://www.ohwr.org/project/gn4124-core/tree/v3.0.1

Fixed
-----
- hdl: L2P DMA issues reported with slower hosts

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

The FIFO size and full threshold need to be enough to hold if necessary all the pending read data
requests from the WB slave.

In the case of the Spartan-6 DDR controller being the WB slave, the FIFO needs to be able to store
up to 192 words (128 from the controller itself, plus 64 from our wrapper).

Since the GN4124 is used primarily on the SPEC, this is now the default value for the L2P DMA
master.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This bug was not affecting the design, as it would read once from an empty FIFO only after
the transfer was done.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This commit fixes an issue that would cause the L2P DMA to drop some data when the WB slave would
stall at the same cycle as the dual-clock FIFO would raise the 'full' flag.

The WB state machine has been redesigned in order to solve this issue and make sure that data is
properly retained when this condition appears.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

3.0.0 - 2020-07-27
==================
https://www.ohwr.org/project/gn4124-core/tree/v3.0.0

Added
-----
- hdl: SystemVerilog BFM and testbench.
- hdl: Add wrapper with wishbone records and slave adapters.
- hdl: Add generics to tune the depths of the various async FIFOs.

Changed
-------
- hdl: Major rewrite of DMA engine, in particular the L2P DMA Master.
- hdl: Major cleanup of resets and cross-clock domain synchronisation.
- hdl: Stop using coregen FIFOs, switch to FIFOs from general-cores.
- hdl: Make DMA optional (g_WITH_DMA generic).
- hdl: Use cheby to describe registers, only one interrupt (level).
- hdl: Test, verify and enable byte swap feature.
- hdl: Extend SV BFM with tasks to read/write from simulated host memory.

Fixed
-----
- hdl: Fixed incorrect 64-bit DMA transaction generation bug.
- hdl: Allow larger DMA reads (up to the full 32 bits of the "length" register) for L2P DMA master.
- hdl: Add flow control to the write buffer of the BFM to prevent overflows during 'wr' commands.
- hdl: Fix swapped bits in attributes.
- hdl: Handle host 32-bit address overflow in L2P DMA master.
- hdl: Fix bug in BFM not respecting P2L_RDY during DMA writes.
- hdl: Fix bug in BFM not accepting 4096B writes.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Remove the option to use the 200MHz PCI clock for the complete DMA engine to avoid compicating the design
and introducing too many alternatives that will need to be tested, now and in the future.

On the SPEC, it has been shown that with the latest modifications it is trivial to meet timing when using
a 125MHz (asynchronous to the PCI) clock for DMA.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>