p2l_dma_master: refactoring.

Remove unused signals, renaming.

hdl/rtl/p2l_dma_master.vhd

@@ -172,13 +172,8 @@ architecture arch of p2l_dma_master is
 
   -- wishbone
   signal wb_ack_cnt      : unsigned(15 downto 0);
-  signal p2l_dma_cyc_t   : std_logic;
-  signal p2l_dma_stb_t   : std_logic;
-  signal p2l_dma_tfr     : boolean;
-  signal p2l_dma_stall_d : std_logic_vector(1 downto 0)  := (others => '0');
-  signal p2l_dma_sel_t   : std_logic_vector(3 downto 0)  := (others => '0');
-  signal p2l_dma_adr_t   : std_logic_vector(31 downto 0) := (others => '0');
-  signal p2l_dma_dat_t   : std_logic_vector(31 downto 0) := (others => '0');
+  signal wb_dma_out_stb  : std_logic;
+  signal wb_dma_tfr     : boolean;
 
   -- P2L DMA read request FSM
   type p2l_dma_state_type is (P2L_IDLE, P2L_HEADER, P2L_ADDR_H, P2L_ADDR_L, P2L_WAIT_READ_COMPLETION);
@@ -197,8 +192,6 @@ architecture arch of p2l_dma_master is
   signal to_wb_fifo_full_next : std_logic;
 
 begin
-
-
   -- Errors to DMA controller
   dma_ctrl_error_o <= dma_busy_error or completion_error;
 
@@ -400,16 +393,6 @@ begin
     end if;
   end process p_ctrl_pipe;
 
-  -- NOTE: this pipeline was here before the reset and resync rehaul,
-  -- however it was clocked by the wrong clock (clk_i).
-  p_dma_stall_d2 : process (wb_dma_clk_i)
-  begin
-    if rising_edge(wb_dma_clk_i) then
-      p2l_dma_stall_d(0) <= wb_dma_i.stall;
-      p2l_dma_stall_d(1) <= p2l_dma_stall_d(0);
-    end if;
-  end process p_dma_stall_d2;
-
   ------------------------------------------------------------------------------
   -- Received data counter
   ------------------------------------------------------------------------------
@@ -577,65 +560,59 @@ begin
 
   -- write only
   wb_dma_o.we <= '1';
-  p2l_dma_sel_t <= (others => '1');
+  wb_dma_o.sel <= (others => '1');
+  wb_dma_o.stb <= wb_dma_out_stb;
 
   --  Set when a wishbone transfer occurred.
-  p2l_dma_tfr <= p2l_dma_stb_t = '1' and wb_dma_i.stall = '0';
+  wb_dma_tfr <= wb_dma_out_stb = '1' and wb_dma_i.stall = '0';
 
   --  Read from fifo.
   --  Only when the fifo is not empty
   --  and either no previous data or previous data read.
-  --  p2l_dma_stb_t = '1' when there are previous data.
-  to_wb_fifo_rd <= '1' when to_wb_fifo_empty = '0' and (p2l_dma_tfr or p2l_dma_stb_t = '0') else '0';
+  --  wb_dma_out_stb = '1' when there are previous data.
+  to_wb_fifo_rd <= '1' when to_wb_fifo_empty = '0' and (wb_dma_tfr or wb_dma_out_stb = '0') else '0';
 
   -- Wishbone master process
   p_wb_master : process (wb_dma_clk_i)
   begin
     if rising_edge(wb_dma_clk_i) then
       if wb_fifo_rst_n = '0' then
-        p2l_dma_cyc_t <= '0';
-        p2l_dma_stb_t <= '0';
+        wb_dma_o.cyc <= '0';
+        wb_dma_out_stb <= '0';
         wb_ack_cnt <= (others => '0');
       else
         if to_wb_fifo_rd = '1' then
           --  Data available, read them from the fifo.
-          p2l_dma_adr_t(31 downto 30) <= "00";
-          p2l_dma_adr_t(29 downto 0)  <= to_wb_fifo_dout(61 downto 32);
-          p2l_dma_dat_t               <= to_wb_fifo_dout(31 downto 0);
+          wb_dma_o.adr(31 downto 30) <= "00";
+          wb_dma_o.adr(29 downto 0)  <= to_wb_fifo_dout(61 downto 32);
+          wb_dma_o.dat               <= to_wb_fifo_dout(31 downto 0);
 
           -- Data/addresses are valid when fifo was just read.
-          p2l_dma_stb_t <= '1';
-          p2l_dma_cyc_t <= '1';
+          wb_dma_out_stb <= '1';
+          wb_dma_o.cyc <= '1';
         else
           --  No read.
-          if p2l_dma_stb_t = '1' and wb_dma_i.stall = '1' then
+          if wb_dma_out_stb = '1' and wb_dma_i.stall = '1' then
             --  Data were not read, just wait.
             null;
           elsif to_wb_fifo_empty = '1' then
             --  No more data to produce.
-            p2l_dma_stb_t <= '0';
+            wb_dma_out_stb <= '0';
 
             if wb_ack_cnt = 0 then
               --  End of the burst
-              p2l_dma_cyc_t <= '0';
+              wb_dma_o.cyc <= '0';
             end if;
           end if;
         end if;
 
         --  Track number of expected ack.
-        if p2l_dma_tfr and wb_dma_i.ack = '0' then
+        if wb_dma_tfr and wb_dma_i.ack = '0' then
           wb_ack_cnt <= wb_ack_cnt + 1;
-        elsif not p2l_dma_tfr and wb_dma_i.ack = '1' then
+        elsif not wb_dma_tfr and wb_dma_i.ack = '1' then
           wb_ack_cnt <= wb_ack_cnt - 1;
         end if;
       end if;
     end if;
   end process p_wb_master;
-
-  -- for read back
-  wb_dma_o.cyc <= p2l_dma_cyc_t;
-  wb_dma_o.stb <= p2l_dma_stb_t;
-  wb_dma_o.sel <= p2l_dma_sel_t;
-  wb_dma_o.adr <= p2l_dma_adr_t;
-  wb_dma_o.dat <= p2l_dma_dat_t;
 end architecture arch;