l2p_dma_master: simplify the FSM

hdl/rtl/l2p_dma_master.vhd

@@ -98,7 +98,7 @@ architecture arch of l2p_dma_master is
   type l2p_dma_state_type is (L2P_IDLE, L2P_WB_SETUP, L2P_SETUP,
                               L2P_WAIT, L2P_HEADER, L2P_HOLD,
                               L2P_ADDR_H, L2P_ADDR_L, L2P_DATA,
-                              L2P_NEXT, L2P_ERROR);
+                              L2P_ERROR);
   signal l2p_dma_current_state : l2p_dma_state_type := L2P_IDLE;
 
   type wb_dma_state_type is (WB_IDLE, WB_SETUP, WB_DATA, WB_WAIT_ACK);
@@ -222,9 +222,11 @@ begin
             -- constant declaration).
             if dma_total_len > c_L2P_MAX_PAYLOAD then
               dma_packet_len  <= to_unsigned(c_L2P_MAX_PAYLOAD, dma_packet_len'length);
+              dma_total_len   <= dma_total_len - c_L2P_MAX_PAYLOAD;
               dma_last_packet <= '0';
             else
               dma_packet_len  <= dma_total_len(5 downto 0);
+              dma_total_len   <= (others => '0');
               dma_last_packet <= '1';
             end if;
             l2p_dma_current_state <= L2P_WAIT;
@@ -281,20 +283,15 @@ begin
             -- Already checked data_fifo_empty flag during L2P_WAIT.
             -- Start readout here to get first data out on the next cycle.
             data_fifo_rd          <= '1';
+            --  Update host address (for the next transfer)
+            dma_host_addr         <= dma_host_addr + 4*c_L2P_MAX_PAYLOAD;
             l2p_dma_current_state <= L2P_DATA;
 
-          when L2P_HOLD =>
-            l2p_fsm_dframe <= '1';
-            l2p_fsm_valid  <= '0';
-            if data_fifo_empty = '0' and l2p_rdy_i = '1' then
-              data_fifo_rd          <= '1';
-              l2p_dma_current_state <= L2P_DATA;
-            end if;
-
           when L2P_DATA =>
             l2p_fsm_dframe <= '1';
             -- Data FIFO readout
             if data_fifo_empty = '1' or l2p_rdy_i = '0' then
+              --  Not ready - wait
               l2p_dma_current_state <= L2P_HOLD;
             else
               data_fifo_rd   <= '1';
@@ -306,9 +303,8 @@ begin
                 l2p_fsm_dframe <= '0';
                 data_fifo_rd   <= '0';
                 if dma_last_packet = '0' then
-                  l2p_dma_current_state <= L2P_NEXT;
+                  l2p_dma_current_state <= L2P_SETUP;
                 else
-                  dma_total_len         <= (others => '0');
                   l2p_dma_current_state <= L2P_IDLE;
                   dma_ctrl_done_o       <= '1';
                 end if;
@@ -325,11 +321,13 @@ begin
               l2p_dma_current_state <= L2P_ERROR;
             end if;
 
-          when L2P_NEXT =>
-            dma_total_len         <= dma_total_len - c_L2P_MAX_PAYLOAD;
-            dma_target_addr       <= dma_target_addr + c_L2P_MAX_PAYLOAD;
-            dma_host_addr         <= dma_host_addr + 4*c_L2P_MAX_PAYLOAD;
-            l2p_dma_current_state <= L2P_SETUP;
+          when L2P_HOLD =>
+            l2p_fsm_dframe <= '1';
+            l2p_fsm_valid  <= '0';
+            if data_fifo_empty = '0' and l2p_rdy_i = '1' then
+              data_fifo_rd          <= '1';
+              l2p_dma_current_state <= L2P_DATA;
+            end if;
 
           when L2P_ERROR =>
             wb_dma_fsm_en         <= '0';
@@ -354,6 +352,7 @@ begin
 -- Wishbone Master (in the Wishbone clock domain)
 -------------------------------------------------
 
+  --  Info crossing clocks domains (GN -> DDR) at the start of a dma transfer.
   dma_param_to_sync(59 downto 30) <= std_logic_vector(dma_target_addr);
   dma_param_to_sync(29 downto 0)  <= std_logic_vector(dma_total_len);