Add AXI4 slave RTL and testbench
testbench is parameterised to simplify testing with / without AXI and WB_DMA update style on most files
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- hdl/rtl/Manifest.py 10 additions, 0 deletionshdl/rtl/Manifest.py
- hdl/rtl/dma_controller.vhd 1 addition, 1 deletionhdl/rtl/dma_controller.vhd
- hdl/rtl/gn4124_axi4_pkg.vhd 422 additions, 0 deletionshdl/rtl/gn4124_axi4_pkg.vhd
- hdl/rtl/gn4124_axi_r_chl_dcfifo.vhd 166 additions, 0 deletionshdl/rtl/gn4124_axi_r_chl_dcfifo.vhd
- hdl/rtl/gn4124_axi_stream_dcfifo.vhd 157 additions, 0 deletionshdl/rtl/gn4124_axi_stream_dcfifo.vhd
- hdl/rtl/l2p_arbiter.vhd 100 additions, 114 deletionshdl/rtl/l2p_arbiter.vhd
- hdl/rtl/l2p_axi4_wr_dc.vhd 378 additions, 0 deletionshdl/rtl/l2p_axi4_wr_dc.vhd
- hdl/rtl/l2p_axi4_wr_initiator.vhd 415 additions, 0 deletionshdl/rtl/l2p_axi4_wr_initiator.vhd
- hdl/rtl/l2p_axi4_wr_preprocessor.vhd 561 additions, 0 deletionshdl/rtl/l2p_axi4_wr_preprocessor.vhd
- hdl/rtl/l2p_dma_master.vhd 26 additions, 29 deletionshdl/rtl/l2p_dma_master.vhd
- hdl/rtl/p2l_axi4_rd_dc.vhd 367 additions, 0 deletionshdl/rtl/p2l_axi4_rd_dc.vhd
- hdl/rtl/p2l_axi4_rd_initiator.vhd 516 additions, 0 deletionshdl/rtl/p2l_axi4_rd_initiator.vhd
- hdl/rtl/p2l_axi4_rd_preprocessor.vhd 272 additions, 0 deletionshdl/rtl/p2l_axi4_rd_preprocessor.vhd
- hdl/rtl/p2l_decode32.vhd 25 additions, 25 deletionshdl/rtl/p2l_decode32.vhd
- hdl/rtl/p2l_dma_master.vhd 46 additions, 46 deletionshdl/rtl/p2l_dma_master.vhd
- hdl/rtl/rl0_pl_stage_flowcontrol_srst.vhd 145 additions, 0 deletionshdl/rtl/rl0_pl_stage_flowcontrol_srst.vhd
- hdl/rtl/spartan6/gn4124_core.vhd 338 additions, 108 deletionshdl/rtl/spartan6/gn4124_core.vhd
- hdl/rtl/spartan6/gn4124_core_pkg.vhd 196 additions, 12 deletionshdl/rtl/spartan6/gn4124_core_pkg.vhd
- hdl/rtl/spartan6/xwb_gn4124_core.vhd 156 additions, 64 deletionshdl/rtl/spartan6/xwb_gn4124_core.vhd
- hdl/rtl/wbmaster32.vhd 60 additions, 58 deletionshdl/rtl/wbmaster32.vhd
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