New function expects textfile with binary representation of each word in a
separate line, e.g.:
10011000000000000000000000000000
11010000000000000000000000000000
11010000001000000000000000000000
01111000000000010000000000000000
00111000001000010000000000000000

This for example reduces WRPC SPEC reference design synthesis time from ~26
minutes to ~11 minutes.

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

wb_onewire_master: propagated CDR_N/O generics up the hierarchy; added assignments to (new) unspecified WB signals
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

common/gc_i2c_slave: added option to allow automatic ACK of address byte without external user intervention

This was due to a bug in the f_string2bits() which took the commit ID as a string argument, assuming that the character array of the string is (32 downto 1), while in fact the commit_id is a string(1 to 32).

f_string2bits() is now  more resilient, it works with both "up" and "downto" string arguments, by checking the "ascending" attribute of the string type.

gc_frequency_meter: use gc_pulse_synchronizer for external PPS pulse (in case the measured frequency is slower than the gating frequency)

Signed-off-by: Maciej Lipinski <maciej.lipinski@cern.ch>

It seems that similar modules might be needed in other designs. The
added gc_async_signals_input_stage provides:
- synchronisation of input digital asynchronous pulses with the clock
- degliching (filter len config through generic)
- single-clock pulse generation
- extended pulses generation (config through generic)

The new gc_single_reset_gen can generate a single reset signal that
is synchronous with the system clock domain (input clk). The input
to the module is a vector of asynchronous reset signals, such as
PCIe reset or button. These input signals are synchronised with
the clock domain. Additionally, the powerup count-down is taken care
for by the module. The resulting single reset signal is passed through
a programmable number of flip-flops at the output (g_out_reg_depth)
so that the ISE optimizer has easier work with the global reset
funout.

This module is a generalized and (hopefully) improved version of the
spec_reset_gen.vhd that is copy+pasted into many SPEC-based designed.
It was suggested during a review of one of such designes that this
reset should be added to general-cores. This is the execution of this
feedback.

This module might be potentially integrated with the other available
reset-generation module (gc_reset.vhd).