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Platform-independent core collection
Commit c2e0159c authored by Jan Pospisil's avatar Jan Pospisil Committed by Dimitris Lampridis
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hdl: added default values for determined start-up state 

Signed-off-by: 's avatarDimitris Lampridis <Dimitris.Lampridis@cern.ch>
parent f4f85996
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Showing with 76 additions and 64 deletions
modules/common/gc_bicolor_led_ctrl.vhd
View file @ c2e0159c
......@@ -107,12 +107,12 @@ architecture rtl of gc_bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_refresh_cnt_nb_bits - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_refresh_cnt_nb_bits - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_line_oen_cnt_nb_bits - 1 downto 0);
signal refresh_rate_cnt : unsigned(c_refresh_cnt_nb_bits - 1 downto 0) := (others => '0');
signal refresh_rate : std_logic := '0';
signal line_ctrl : std_logic := '0';
signal intensity_ctrl_cnt : unsigned(c_refresh_cnt_nb_bits - 1 downto 0) := (others => '0');
signal intensity_ctrl : std_logic := '0';
signal line_oen_cnt : unsigned(c_line_oen_cnt_nb_bits - 1 downto 0) := (others => '0');
signal line_oen : std_logic_vector(2**c_line_oen_cnt_nb_bits - 1 downto 0);
signal led_state : std_logic_vector((g_nb_line * g_nb_column) -1 downto 0);
......
modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
View file @ c2e0159c
......@@ -154,12 +154,12 @@ entity i2c_master_bit_ctrl is
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
cmd_ack : out std_logic := '0'; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
dout : out std_logic := '0';
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
......@@ -180,17 +180,19 @@ architecture structural of i2c_master_bit_ctrl is
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA
signal clk_en : std_logic; -- statemachine clock enable
signal scl_sync, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
signal c_state : states := idle;
signal iscl_oen, isda_oen : std_logic := '1'; -- internal I2C lines
signal sda_chk : std_logic := '0'; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic := '0'; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic := '1'; -- synchronized SCL and SDA inputs
signal dSCL, dSDA : std_logic := '1'; -- delayed versions ofsSCL and sSDA
signal clk_en : std_logic := '1'; -- statemachine clock enable
signal scl_sync : std_logic; -- clock generation signals
signal slave_wait : std_logic := '0'; -- clock generation signals
signal ial : std_logic := '0'; -- internal arbitration lost signal
signal cnt : unsigned(15 downto 0) := (others => '0');
-- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
......@@ -242,13 +244,16 @@ begin
-- generate bus status controller
bus_status_ctrl: block
signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL
signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA
signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
signal cSCL, cSDA : std_logic_vector( 1 downto 0) := "00";
-- capture SDA and SCL
signal fSCL, fSDA : std_logic_vector( 2 downto 0) := (others => '1');
-- filter inputs for SCL and SDA
signal filter_cnt : unsigned(13 downto 0) := (others => '0');
-- clock divider for filter
signal sta_condition : std_logic := '0'; -- start detected
signal sto_condition : std_logic := '0'; -- stop detected
signal cmd_stop : std_logic := '0'; -- STOP command
signal ibusy : std_logic := '0'; -- internal busy signal
begin
-- capture SCL and SDA
capture_scl_sda: process(clk, nReset)
......
modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
View file @ c2e0159c
......@@ -86,16 +86,16 @@ entity i2c_master_byte_ctrl is
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
ack_out : out std_logic := '0';
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
......@@ -146,20 +146,22 @@ architecture structural of i2c_master_byte_ctrl is
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal core_cmd : std_logic_vector(3 downto 0) := I2C_CMD_NOP;
signal core_ack, core_rxd : std_logic;
signal core_txd : std_logic := '0';
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
signal sr : std_logic_vector(7 downto 0) := (others => '0'); -- 8bit shift register
signal shift, ld : std_logic := '0';
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal go: std_logic;
signal host_ack : std_logic := '0';
signal dcnt : unsigned(2 downto 0) := (others => '0'); -- data counter
signal cnt_done : std_logic;
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states := st_idle;
begin
-- hookup bit_controller
......
modules/wishbone/wb_i2c_master/i2c_master_top.vhd
View file @ c2e0159c
......@@ -88,12 +88,13 @@ entity i2c_master_top is
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_dat_o : out std_logic_vector(7 downto 0) := (others => '0');
-- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
wb_inta_o : out std_logic := '0'; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0); -- i2c clock line input
......@@ -141,13 +142,13 @@ architecture structural of i2c_master_top is
end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
signal prer : unsigned(15 downto 0) := (others => '1'); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0) := (others => '0'); -- control register
signal txr : std_logic_vector(7 downto 0) := (others => '0'); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0) := (others => '0'); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
......@@ -155,7 +156,7 @@ architecture structural of i2c_master_top is
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
signal iack_o : std_logic := '0';
-- done signal: command completed, clear command register
signal done : std_logic;
......@@ -167,16 +168,18 @@ architecture structural of i2c_master_top is
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal irxack : std_logic; -- received aknowledge from slave
signal rxack : std_logic := '0'; -- received aknowledge from slave
signal tip : std_logic := '0'; -- transfer in progress
signal irq_flag : std_logic := '0'; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
signal al : std_logic := '0'; -- arbitration lost
signal i2c_al : std_logic; -- arbitration lost
signal scl_in, scl_out, scl_oen : std_logic;
signal sda_in, sda_out, sda_oen : std_logic;
signal if_num : std_logic_vector(3 downto 0);
signal if_busy : std_logic;
signal if_num : std_logic_vector(3 downto 0) := (others => '0');
signal if_busy : std_logic := '0';
begin
-- generate internal reset signal
......
modules/wishbone/wb_spi/spi_clgen.v
View file @ c2e0159c
......@@ -56,7 +56,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg clk_out = 1'b0;
reg pos_edge;
reg neg_edge;
......
modules/wishbone/wb_spi/spi_shift.v
View file @ c2e0159c
......@@ -69,8 +69,8 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg s_out = 1'b0;
reg tip = 1'b0;
reg [SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [SPI_MAX_CHAR-1:0] data; // shift register
......
modules/wishbone/wb_spi/spi_top.v
View file @ c2e0159c
......@@ -86,14 +86,16 @@ module spi_top
output mosi_pad_o; // master out slave in
input miso_pad_i; // master in slave out
reg [32-1:0] wb_dat_o;
reg wb_ack_o;
reg wb_int_o;
reg [32-1:0] wb_dat_o = 32'b0;
reg wb_ack_o = 1'b0;
reg wb_int_o = 1'b0;
// Internal signals
reg [SPI_DIVIDER_LEN-1:0] divider; // Divider register
reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
reg [SPI_SS_NB-1:0] ss; // Slave select register
reg [`SPI_CTRL_BIT_NB-1:0] ctrl = {`SPI_CTRL_BIT_NB{1'b0}};
// Control and status register
reg [SPI_SS_NB-1:0] ss = {SPI_SS_NB{1'b0}};
// Slave select register
reg [32-1:0] wb_dat; // wb data out
wire [SPI_MAX_CHAR-1:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
......
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