- 11 Mar, 2020 1 commit
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Tristan Gingold authored
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- 06 Mar, 2020 4 commits
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Dimitris Lampridis authoredSigned-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Dimitris Lampridis authored
Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Dimitris Lampridis authored
Also perform cleanup of sync and edge modules. Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Tomasz Wlostowski authored
Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 05 Mar, 2020 6 commits
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Tristan Gingold authored
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Dimitris Lampridis authored
Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Dimitris Lampridis authored
Reported by Olof Olof Kindgren (@olofk). See also merge request !4. Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Dimitris Lampridis authored
This allows them to be used right after in component declarations. Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Dimitris Lampridis authored
This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it much easier for ISE 14.7 to reach timing closure. It also helps in general to ensure that the synchronisation structures remain intact and do not get merged in unpredictable ways with other parts of the design. Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch> -
Dimitris Lampridis authored
Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 04 Mar, 2020 1 commit
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Tristan Gingold authored
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- 03 Mar, 2020 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 19 Feb, 2020 2 commits
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Christos Gentsos authored
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Christos Gentsos authored
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- 17 Feb, 2020 1 commit
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Dimitris Lampridis authored
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- 30 Jan, 2020 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 17 Jan, 2020 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
The WB master interface has been re-written, in order to improve performance, compatibility with the "standard" and code readability. The new interface has been successfully verified with existing testbenches from the following projects: * wr-cores * wr-switch-hdl * mockturtle * ddr3-sp6-core * fmc-adc-100m14b4cha Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch>
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- 15 Jan, 2020 3 commits
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by:Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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- 13 Dec, 2019 1 commit
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Dimitris Lampridis authored
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- 24 Oct, 2019 6 commits
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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- 23 Oct, 2019 3 commits
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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- 22 Oct, 2019 5 commits
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
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