This is done to better reflect the interface of the module (structured Wishbone).
The documentation of the module is also changed in this respect.

If a very fast WB master queues a single-byte SPI command followed
immediately by the execute instruction, the SPI command will use
the old data in the FIFO. This delays execution by 1 cycle.

It was causing the simulation to fail with designs containing a xwb_register_link component.

Use a counter instead of a shift register + comparator.

It is based on gc_glitch_filt, but with the glitch filter length
dynamically progammable via a port.

Using the volatile configuration register to configure a flash chip
is a bad idea. The problem is that if the FPGA is reset, the flash
may be in a state inconsistent with what the FPGA requires to boot.

The correct solution is to configure the non-volatile configuration
register on the chip to what the FPGA expects on power-on. Then use
these same settings inside the flash core.

Going this route makes it necessary for software to be able to set
the non-volatile configuration register. Rather than making the core
even more complicated than it is, I have elected to add a FIFO which
software can fill to issue custom SPI commands. Since erase can only
be done from software anyway, I removed this code and let erase use
the custom command FIFO.

Comparing std_logic <= '0' seems to work!
However, it is certainly not what the author intended.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

This is done by adding a generic to the entity, which is connected directly to
the gc_fsm_watchdog component instantiated within the wb_i2c_bridge. The user
should calculate the appropriate watchdog timeout value and set it via this
generic.

The instantiation template in the wishbone_pkg is also updated.
Signed-off-by: Theodor Stana <t.stana@cern.ch>

To make the design more modular, moved the synchronization chain out of
the gc_glitch_filt component. Made the necessary changes in the
components using the gc_glitch_filt.

Also added gc_glitch_filt documentation.
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources

Also updated the rest of the documentation file to have a pretty
regmap.
Signed-off-by: Theodor Stana <t.stana@cern.ch>

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules
Signed-off-by: Theodor Stana <t.stana@cern.ch>

This change is necessary for network control/monitor tool in order to read the GUI command output.
The GUI command output can not be stored into a 1024 bytes fifo.

wb_irq_slave: added clear and enable registers

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>