Commit 382b46c1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Renamed wb_xil_multiboot to xwb_xil_multiboot

This is done to better reflect the interface of the module (structured Wishbone).
The documentation of the module is also changed in this respect.
parent 6e78212a
FILE=wb_xil_multiboot
FILE=xwb_xil_multiboot
all:
$(MAKE) -C fig
......
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill February 13, 2014
\hfill July 31, 2014
\vspace*{3cm}
......
......@@ -996,7 +996,7 @@ package wishbone_pkg is
------------------------------------------------------------------------------
-- MultiBoot component
------------------------------------------------------------------------------
component wb_xil_multiboot is
component xwb_xil_multiboot is
port
(
-- Clock and reset input ports
......@@ -1013,9 +1013,9 @@ package wishbone_pkg is
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component wb_xil_multiboot;
end component xwb_xil_multiboot;
constant c_wb_xil_multiboot_sdb : t_sdb_device := (
constant c_xwb_xil_multiboot_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
......
......@@ -2,5 +2,5 @@ files = [
"spi_master.vhd",
"multiboot_fsm.vhd",
"multiboot_regs.vhd",
"wb_xil_multiboot.vhd"
"xwb_xil_multiboot.vhd"
]
......@@ -43,7 +43,7 @@ use unisim.vcomponents.all;
use work.wishbone_pkg.all;
entity wb_xil_multiboot is
entity xwb_xil_multiboot is
port
(
-- Clock and reset input ports
......@@ -60,10 +60,10 @@ entity wb_xil_multiboot is
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end entity wb_xil_multiboot;
end entity xwb_xil_multiboot;
architecture struct of wb_xil_multiboot is
architecture struct of xwb_xil_multiboot is
--============================================================================
-- Component declarations
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment