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06adc72a
Commit
06adc72a
authored
Mar 28, 2014
by
Theodor-Adrian Stana
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doc: Update wb_i2c_bridge and add colored tables to other modules
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
159e5a99
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6 changed files
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97 additions
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66 deletions
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-66
gc_fsm_watchdog.tex
doc/gc_fsm_watchdog/gc_fsm_watchdog.tex
+13
-10
gc_glitch_filt.tex
doc/gc_glitch_filt/gc_glitch_filt.tex
+4
-1
gc_i2c_slave.tex
doc/gc_i2c_slave/gc_i2c_slave.tex
+7
-1
wb_i2c_bridge.tex
doc/wb_i2c_bridge/wb_i2c_bridge.tex
+60
-41
multiboot-regs.tex
doc/wb_xil_multiboot/multiboot-regs.tex
+1
-1
wb_xil_multiboot.tex
doc/wb_xil_multiboot/wb_xil_multiboot.tex
+12
-12
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doc/gc_fsm_watchdog/gc_fsm_watchdog.tex
View file @
06adc72a
...
...
@@ -6,7 +6,8 @@
\usepackage
{
graphicx
}
\usepackage
{
multirow
}
\usepackage
{
color
}
% Color package
\usepackage
[usenames,dvipsnames,table]
{
xcolor
}
\usepackage
[toc,page]
{
appendix
}
...
...
@@ -36,6 +37,7 @@
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l c p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Date
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Version
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Change
}}
\\
...
...
@@ -87,20 +89,21 @@ in the HDL code to reset the FSM.
The ports of the
\textit
{
gc
\_
fsm
\_
watchdog
}
module are shown in Table~
\ref
{
tbl:ports
}
.
\begin{table}
[h]
\caption
{
Ports of
\textit
{
vbcp
\_
wb
}
module
}
\caption
{
Ports of
\textit
{
gc
\_
fsm
\_
watchdog
}
module
}
\label
{
tbl:ports
}
\centerline
{
\begin{tabular}
{
l c p
{
.6
\textwidth
}}
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l p
{
.8
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Port
}}
&
\textbf
{
Size
}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\multicolumn
{
1
}{
c
}{
\textbf
{
Name
}
}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
clk
\_
i
&
1
&
Clock input
\\
rst
\_
n
\_
i
&
1
&
Active-low reset input
\\
wdt
\_
rst
\_
i
&
1
&
Active-high reset input from the FSM to the watchdog timer
\newline
Synchronous to
\textit
{
clk
\_
i
}
\\
fsm
\_
rst
\_
o
&
1
&
Active-high reset output from the watchdog timer to the FSM
\newline
Synchronous to
\textit
{
clk
\_
i
}
\\
\\
clk
\_
i
&
Clock input
\\
rst
\_
n
\_
i
&
Active-low reset input
\\
wdt
\_
rst
\_
i
&
Active-high reset input from the FSM to the watchdog timer
\newline
Synchronous to
\textit
{
clk
\_
i
}
\\
fsm
\_
rst
\_
o
&
Active-high reset output from the watchdog timer to the FSM
\newline
Synchronous to
\textit
{
clk
\_
i
}
\\
\hline
\end{tabular}
}
...
...
doc/gc_glitch_filt/gc_glitch_filt.tex
View file @
06adc72a
...
...
@@ -4,7 +4,7 @@
\documentclass
[a4paper,11pt]
{
article
}
% Color package
\usepackage
[usenames,dvipsnames
]
{
color
}
\usepackage
[usenames,dvipsnames
,table]
{
x
color
}
% Hyperrefs
\usepackage
[
...
...
@@ -45,6 +45,7 @@
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l c p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Date
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Version
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Change
}}
\\
...
...
@@ -116,6 +117,7 @@ clock cycles later.
\label
{
tbl:ports
}
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l p
{
.7
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Name
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
...
...
@@ -124,6 +126,7 @@ clock cycles later.
1 -- glitches narrower than 1
\textit
{
clk
\_
i
}
cycle are filtered
\newline
2 -- glitches narrower than 2
\textit
{
clk
\_
i
}
cycles are filtered
\newline
etc.
\\
\hline
clk
\_
i
&
Clock input
\\
rst
\_
n
\_
i
&
Active-low reset input
\\
dat
\_
i
&
Data input (should be synchronous to
\textit
{
clk
\_
i
}
)
\\
...
...
doc/gc_i2c_slave/gc_i2c_slave.tex
View file @
06adc72a
...
...
@@ -4,7 +4,7 @@
\documentclass
[a4paper,11pt]
{
article
}
% Color package
\usepackage
[usenames,dvipsnames
]
{
color
}
\usepackage
[usenames,dvipsnames
,table]
{
x
color
}
% Hyperrefs
\usepackage
[
...
...
@@ -45,6 +45,7 @@
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l c p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Date
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Version
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Change
}}
\\
...
...
@@ -163,6 +164,7 @@ To instantiate a tri-state buffer in VHDL:
\label
{
tbl:ports
}
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l p
{
.8
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Name
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
...
...
@@ -171,6 +173,7 @@ To instantiate a tri-state buffer in VHDL:
1 -- glitches narrower than 1
\textit
{
clk
\_
i
}
cycle are filtered
\newline
2 -- glitches narrower than 2
\textit
{
clk
\_
i
}
cycles are filtered
\newline
etc.
\\
\hline
clk
\_
i
&
Clock input
\\
rst
\_
n
\_
i
&
Active-low reset input
\\
scl
\_
i
&
SCL line input
\\
...
...
@@ -391,6 +394,8 @@ Figure~\ref{fig:fsm-and-scl}.
\label
{
fig:fsm-and-scl
}
\end{figure}
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{longtable}
{
l p
{
.7
\textwidth
}}
\caption
{
The states of the
\textit
{
gc
\_
i2c
\_
slave
}
FSM
}
\label
{
tbl:fsm
}
\\
...
...
@@ -425,6 +430,7 @@ Figure~\ref{fig:fsm-and-scl}.
\textit
{
WR
\_
ACK
}
&
Read ACK bit sent by master. If '0', go back to
\textit
{
WR
}
state, otherwise
go to
\textit
{
IDLE
}
state.
\\
\end{longtable}
}
%------------------------------------------------------------------------------
\subsection
{
Output control
}
...
...
doc/wb_i2c_bridge/wb_i2c_bridge.tex
View file @
06adc72a
...
...
@@ -4,7 +4,7 @@
\documentclass
[a4paper,11pt]
{
article
}
% Color package
\usepackage
[usenames,dvipsnames
]
{
color
}
\usepackage
[usenames,dvipsnames
,table]
{
x
color
}
% Appendix package
\usepackage
[toc,page]
{
appendix
}
...
...
@@ -49,6 +49,7 @@
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l c p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Date
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Version
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Change
}}
\\
...
...
@@ -59,7 +60,8 @@
changes in protocol
\\
29-10-2013
&
0.04
&
Changed PDF link colors
\\
18-12-2013
&
1.00
&
Finite version with watchdog timer and robust communication
\\
12-02-2014
&
1.01
&
Removed SIM
_
WB
_
TRANSFER state in FSM
\\
12-02-2014
&
1.01
&
Removed SIM
\_
WB
\_
TRANSFER state from FSM
\\
28-03-2014
&
1.02
&
Added generic for FSM watchdog timeout value
\\
\hline
\end{tabular}
}
...
...
@@ -126,40 +128,43 @@ Figure~\ref{fig:i2c-ports}; Wishbone slaves should be connected to the
Wishbone master interface ports, prefixed with
\textit
{
wbm
}
.
\begin{table}
[hbtp]
\caption
{
Ports of
\textit
{
wb
\_
i2c
\_
bridge
}
module
}
\caption
{
Ports
and generics
of
\textit
{
wb
\_
i2c
\_
bridge
}
module
}
\label
{
tbl:ports
}
\centerline
{
\begin{tabular}
{
l c p
{
.6
\textwidth
}}
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l p
{
.8
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Port
}}
&
\textbf
{
Size
}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\multicolumn
{
1
}{
c
}{
\textbf
{
Name
}
}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
clk
\_
i
&
1
&
Clock input
\\
rst
\_
n
\_
i
&
1
&
Active-low reset input
\\
sda
\_
en
\_
o
&
1
&
SDA line output tri-state enable
\\
sda
\_
i
&
1
&
SDA line input
\\
sda
\_
o
&
1
&
SDA line output
\\
scl
\_
en
\_
o
&
1
&
SCL line tri-state enable
\\
scl
\_
i
&
1
&
SCL line input
\\
scl
\_
o
&
1
&
SCL line output
\\
i2c
\_
addr
\_
i
&
7
&
I
$^
2
$
C slave address on ELMA I
$^
2
$
C bus
\\
tip
\_
o
&
1
&
Transfer In Progress
\newline
'1' -- I
$^
2
$
C address sent by SysMon matches that of the I
$^
2
$
C slave
\newline
'0' -- after transfer has completed and I
$^
2
$
C slave is idle
\\
err
\_
p
\_
o
&
1
&
Error bit, high for one
\textit
{
clk
\_
i
}
cycle when the Wishbone address
the SysMon tries to access is invalid
\\
wdto
\_
p
\_
o
&
1
&
FSM watchdog timer time-out, high for one
\textit
{
clk
\_
i
}
cycle when
the FSM watchdog has timed-out
\\
wbm
\_
stb
\_
o
&
1
&
Wishbone data strobe output
\\
wbm
\_
cyc
\_
o
&
1
&
Wishbone valid cycle output
\\
wbm
\_
sel
\_
o
&
4
&
Wishbone byte select output
\\
wbm
\_
we
\_
o
&
1
&
Wishbone write enable output
\\
wbm
\_
dat
\_
i
&
32
&
Wishbone data input (to master)
\\
wbm
\_
dat
\_
o
&
32
&
Wishbone data output (from master)
\\
wbm
\_
adr
\_
o
&
32
&
Wishbone address output
\\
wbm
\_
ack
\_
i
&
1
&
Wishbone acknowledge signal input
\\
wbm
\_
rty
\_
i
&
1
&
Wishbone retry signal input
\\
wbm
\_
err
\_
i
&
1
&
Wishbone error signal input
\\
g
\_
fsm
\_
wdt
&
Timeout value (in
\textit
{
clk
\_
i
}
cycles) for the FSM watchdog timer
\\
\hline
clk
\_
i
&
Clock input
\\
rst
\_
n
\_
i
&
Active-low reset input
\\
sda
\_
en
\_
o
&
SDA line output tri-state enable
\\
sda
\_
i
&
SDA line input
\\
sda
\_
o
&
SDA line output
\\
scl
\_
en
\_
o
&
SCL line tri-state enable
\\
scl
\_
i
&
SCL line input
\\
scl
\_
o
&
SCL line output
\\
i2c
\_
addr
\_
i
&
I
$^
2
$
C slave address on ELMA I
$^
2
$
C bus
\\
tip
\_
o
&
Transfer In Progress
\newline
'1' -- I
$^
2
$
C address sent by SysMon matches that of the I
$^
2
$
C slave
\newline
'0' -- after transfer has completed and I
$^
2
$
C slave is idle
\\
err
\_
p
\_
o
&
Error bit, high for one
\textit
{
clk
\_
i
}
cycle when the Wishbone address
the SysMon tries to access is invalid
\\
wdto
\_
p
\_
o
&
FSM watchdog timer time-out, high for one
\textit
{
clk
\_
i
}
cycle when
the FSM watchdog has timed-out
\\
wbm
\_
stb
\_
o
&
Wishbone data strobe output
\\
wbm
\_
cyc
\_
o
&
Wishbone valid cycle output
\\
wbm
\_
sel
\_
o
&
Wishbone byte select output
\\
wbm
\_
we
\_
o
&
Wishbone write enable output
\\
wbm
\_
dat
\_
i
&
Wishbone data input (to master)
\\
wbm
\_
dat
\_
o
&
Wishbone data output (from master)
\\
wbm
\_
adr
\_
o
&
Wishbone address output
\\
wbm
\_
ack
\_
i
&
Wishbone acknowledge signal input
\\
wbm
\_
rty
\_
i
&
Wishbone retry signal input
\\
wbm
\_
err
\_
i
&
Wishbone error signal input
\\
\hline
\end{tabular}
}
...
...
@@ -296,6 +301,7 @@ shown in Table~\ref{tbl:cmds}.
\label
{
tbl:cmds
}
\centerline
{
\rowcolors
{
2
}{
white
}{
gray
!
25
}
\begin
{
tabular
}{
l p
{
.
6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Command
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
...
...
@@ -359,6 +365,7 @@ is writing and the \textit{wb\_i2c\_bridge} is reading.
\label
{
tbl:fsm
}
\centerline
{
\rowcolors
{
2
}{
white
}{
gray
!
25
}
\begin
{
tabular
}{
l p
{
.
7
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
State
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
...
...
@@ -429,7 +436,7 @@ state, setting the \textit{err\_p\_o} output for one \textit{clk\_i} cycle.
The design also contains an FSM watchdog component, which resets the main FSM
in case of errors in communication. The watchdog timeout value is configured
via the
\textit
{
g
\_
wdt
\_
max
}
generic and can be calculated as outlined in
via the
\textit
{
g
\_
fsm
\_
wdt
}
generic and can be calculated as outlined in
Appendix~
\ref
{
app:wdto
-
calc
}
.
%==============================================================================
...
...
@@ -445,6 +452,7 @@ on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
\caption
{
Synthesis results
}
\label
{
tbl:synth
-
res
}
\centerline
{
\rowcolors
{
2
}{
white
}{
gray
!
25
}
\begin
{
tabular
}{
l c c c
}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Resource
}}
&
\textbf
{
Used
}
&
\textbf
{
Available
}
&
\textbf
{
\%
}
\\
...
...
@@ -469,20 +477,18 @@ on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
In order to calculate the maximum watchdog timeout value, the following procedure
should be utilized.
First, the frequency on the I
$^
2
$
C communication in ELMA crates is
100
~kHz. One
I
$^
2
$
C byte transfer always consists in
9
bits
(
eight bits for data plus one for
acknowledgement
)
. Therefore, one I
$^
2
$
C byte is transferred within
90
~
$
\mu
$
s.
To account for start and stop conditions and to allow for frequency changes on
the bus, one can consider one I
$^
2
$
C byte as
10
bits, therefore one I
$^
2
$
C
transfer can be considered to take
10
~
$
\mu
$
s to complete.
First, one should consider the bit period on the I
$^
2
$
C transfer,
$
T
_{
bit
}$
. One I
$^
2
$
C
byte transfer consists of
9
bits
(
eight data bits plus one ACK
)
. To account for start
and stop conditions and to allow for frequency changes on the bus, one can consider
one I
$^
2
$
C byte as
10
bits. Therefore, one I
$^
2
$
C transfer can be considered to take
10
*
$
T
_{
bit
}$
to complete.
Now, taking this into account and the period of the
\textit
{
clk
\_
i
}
input,
$
T
_{
clk
\_
i
}$
, the number of clock cycles needed to complete one I
$^
2
$
C byte transfer
can be calculated as:
\begin
{
equation
}
N
_{
byte
}
=
\frac
{
10
{
\mu
}
s
}{
T
_{
clk
\_
i
}}
N
_{
clocks
}
=
\frac
{
10
*
T
_{
bit
}
}{
T
_{
clk
\_
i
}}
\end
{
equation
}
Within the ELMA crates, a maximum of
35
bytes can be sent through I
$^
2
$
C. This
...
...
@@ -493,9 +499,22 @@ maximum watchdog timeout value to be the time needed to send 40 bytes via I$^2$C
on the bus:
\begin
{
equation
}
g
\_
wdt
\_
max
=
40
*
N
_{
byte
}
=
40
*
\frac
{
10
{
\mu
}
s
}{
T
_{
clk
\_
i
}}
g
\_
fsm
\_
wdt
=
40
*
N
_{
clocks
}
=
40
*
\frac
{
10
*
T
_{
bit
}}{
T
_{
clk
\_
i
}}
\end
{
equation
}
It is good practice to increase this value even further, to account for changes
in bit widths, etc.
For example, in converter board designs, where
$
T
_{
clk
}
= 50ns
$
, the
\textit
{
g
\_
fsm
\_
wdt
}
value was calculated based on
$
T
_{
bit
}
= 30
{
\mu
}
s
$
.
The final value was doubled to account for potential changes in the bit period:
\begin
{
equation
}
g
\_
fsm
\_
wdt
=
2
*
\left
(
40
*
\frac
{
10
*
30
{
\mu
}
s
}{
50
ns
}
\right
)
=
2
*
240000
=
480000
\end
{
equation
}
This results in that the FSM watchdog would time out in
24
~ms.
\end
{
appendices
}
%==============================================================================
...
...
doc/wb_xil_multiboot/multiboot-regs.tex
View file @
06adc72a
...
...
@@ -5,7 +5,7 @@
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{longtable}
{
l l l p
{
.5
\textwidth
}}
\hline
\textbf
{
Offset
}
&
\textbf
{
Defaul
t
}
&
\textbf
{
Name
}
\textbf
{
Offset
}
&
\textbf
{
Rese
t
}
&
\textbf
{
Name
}
&
\textbf
{
Description
}
\\
\hline
\endfirsthead
...
...
doc/wb_xil_multiboot/wb_xil_multiboot.tex
View file @
06adc72a
...
...
@@ -175,18 +175,18 @@ connected directly to the FPGA output ports connected to the flash chip.
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l
c
p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Port
}}
&
\
textbf
{
Size
}
&
\
multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
clk
\_
i
&
1
&
Clock input (max. 20~MHz)
\\
rst
\_
n
\_
i
&
1
&
Active-low reset input
\\
wbs
\_
i
&
&
Wishbone slave interface inputs
\\
wbs
\_
o
&
&
Wishbone slave interface outputs
\\
spi
\_
cs
\_
n
\_
o
&
1
&
Active-low chip select output
\\
spi
\_
sclk
\_
o
&
1
&
SPI clock output
\\
spi
\_
mosi
\_
o
&
1
&
SPI data output line (Master Out, Serial In)
\\
spi
\_
miso
\_
i
&
1
&
SPI data input line (Master In, Serial Out)
\\
\begin{tabular}
{
l p
{
.6
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
Port
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
clk
\_
i
&
Clock input (max. 20~MHz)
\\
rst
\_
n
\_
i
&
Active-low reset input
\\
wbs
\_
i
&
Wishbone slave interface inputs
\\
wbs
\_
o
&
Wishbone slave interface outputs
\\
spi
\_
cs
\_
n
\_
o
&
Active-low chip select output
\\
spi
\_
sclk
\_
o
&
SPI clock output
\\
spi
\_
mosi
\_
o
&
SPI data output line (Master Out, Serial In)
\\
spi
\_
miso
\_
i
&
SPI data input line (Master In, Serial Out)
\\
\hline
\end{tabular}
}
...
...
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