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Commit c63535f0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana Committed by Tomasz Wlostowski
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i2c-bridge: Updated bridge and slave modules 

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent e848b421
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doc/gc_i2c_slave/gc_i2c_slave.tex
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......@@ -372,10 +372,11 @@ Figure~\ref{fig:fsm-diag} shows a simplified state transition diagram of the FSM
and Table~\ref{tbl:fsm} lists the states of the FSM and the operations performed in each
state. Across the FSM, shifting of bits into the module is done on the rising edge
of SCL and shifting out is done on the falling edge of SCL. A three-bit counter is
used to count the number of received bits. This bit counter is incremented on the
rising edge of SCL. During read and write cycles, the FSM also changes states on
the SCL falling edge. A summary of the FSM actions with reference to the SCL line
on read and write transfer is shown in Figure~\ref{fig:fsm-and-scl}.
used to count the number of bits that are sent and received by the module. This bit
counter is incremented on the rising edge of SCL. During read and write cycles, the
FSM changes states on the SCL falling edge. A summary of the FSM actions with
reference to the SCL line on read and write transfer is shown in
Figure~\ref{fig:fsm-and-scl}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/fsm-diag}}
......@@ -409,8 +410,6 @@ on read and write transfer is shown in Figure~\ref{fig:fsm-and-scl}.
\textit{IDLE} & Default state after reset and the state returned to after
reception of a start and stop condition. \\
\textit{ADDR} & Shift in the address and R/W bit. \\
\textit{ADDR\_CHECK} & Check the address versus \textit{i2c\_addr\_i} and set the \textit{op\_o}
output as per the R/W bit. \\
\textit{ADDR\_ACK} & Send ACK depending on value of \textit{ack\_i} and go to \textit{RD} state
if the R/W bit is high, or to \textit{WR\_LOAD\_TXSR} state if R/W bit is low.
If \textit{ack\_i} is low, go back to \textit{IDLE}. \\
......
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......
doc/wb_i2c_bridge/wb_i2c_bridge.tex
View file @ c63535f0
......@@ -301,10 +301,9 @@ shown in Table~\ref{tbl:cmds}.
\hline
writereg \textit{slot addr val} & Writes the \textit{hex} value \textit{val} to hex address
\textit{addr} of board in slot number \textit{slot} \\
writemregs \textit{slot addr v1 .. v8} & This command is similar to the \textit{writereg}
command, but it allows writing up to eight different values
to the same Wishbone register. The values are given in hexadecimal
format and are separated by spaces \\
writemregs \textit{slot addr v1 .. v8} & Similar to the \textit{writereg} command, but allows writing up to
eight different values to the same Wishbone register. The values
are given in hexadecimal format and are separated by spaces \\
readreg \textit{slot addr} & Returns the value of register at hex address \textit{addr} of
board in slot number \textit{slot} \\
\hline
......@@ -333,7 +332,7 @@ As Figure~\ref{fig:writemregs} shows, the data words are sent in little-endian o
word 0 is sent first, followed by word 1 and so forth, until word 7.
\begin{figure}[h]
\centerline{\includegraphics[scale=.55]{fig/fsm}}
\centerline{\includegraphics[width=\textwidth]{fig/fsm}}
\caption{Main FSM of \textit{wb\_i2c\_bridge} module}
\label{fig:fsm}
\end{figure}
......@@ -341,7 +340,6 @@ word 0 is sent first, followed by word 1 and so forth, until word 7.
%==============================================================================
% SEC: Implem
%==============================================================================
\pagebreak
\section{Implementation}
\label{sec:implem}
......@@ -367,11 +365,7 @@ is writing and the \textit{wb\_i2c\_bridge} is reading.
IDLE & Wait for the \textit{gc\_i2c\_slave} module to receive the I$^2$C
address and go to \textit{WB\_ADR} \\
WB\_ADR & Shift in the two address bytes sent via I$^2$C and go to
\textit{SIM\_WB\_TRANSF} \\
SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous
state and go to \textit{OPER} if Wishbone address exists (Wishbone
\textit{ack} received), or \textit{IDLE} otherwise (Wishbone \textit{err}
received) \\
\textit{OPER} \\
OPER & Check the \textit{op\_o} output of the \textit{gc\_i2c\_slave} module.
If '1', go to \textit{SYSMON\_RD\_WB} state (SysMon is reading from
\textit{wb\_i2c\_bridge}), otherwise continue shifting in bytes (SysMon
......@@ -379,8 +373,10 @@ is writing and the \textit{wb\_i2c\_bridge} is reading.
SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to
\textit{SYSMON\_WR\_WB}\\
SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in
\textit{WB\_ADR} \\
SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in
\textit{WB\_ADR}. If the transfer is successful, go back to \textit{SYSMON\_WR}
to continue receiving register data (useful for the \textit{writemregs} command
-- see Section~\ref{sec:elma-prot-cmds}) \\
SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in
\textit{WB\_ADR} and go to \textit{SYSMON\_RD} \\
SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{gc\_i2c\_slave}
module successfully finishes a write \\
......@@ -396,15 +392,10 @@ during reads and writes from the SysMon.
When the SysMon writes (Figure~\ref{fig:sysmon-wr-fsm}), the
\textit{wb\_i2c\_bridge} module waits in the \textit{IDLE} state until
the I$^2$C address is received, then, while in the \textit{WB\_ADR} state,
it shifts in the Wishbone address. A Wishbone simulation transfer is performed
from the received address. The simulation transfer is in fact a read transfer
from the address, but the data received from the register is not used in any way.
The purpose of this transfer is only to see if the received address exists, indicated
by a Wishbone \textit{ack} being received as a result of this transfer. If this
\textit{ack} is received, the first byte is shifted in while in the \textit{OPER}
state, followed by the next three bytes while in the \textit{SYSMON\_WR} state. The
register is written to in the \textit{SYSMON\_WR\_WB} state using a Wishbone write
transfer.
it shifts in the Wishbone address. The first byte of the write transfer is shifted
in while in the \textit{OPER} state, followed by the next three bytes while in the
\textit{SYSMON\_WR} state. The register is written to in the \textit{SYSMON\_WR\_WB}
state using a Wishbone write transfer.
To allow for the \textit{writemregs} command, whereby up to eight registers can be
written with one I$^2$C transfer, the FSM goes back to the \textit{SYSMON\_WR} state
......@@ -413,7 +404,7 @@ if the Wishbone write transfer completed successfully. The FSM will go back into
the SysMon after the \textit{writereg} or \textit{writemregs} has been completed.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sysmon-wr-fsm}}
\centerline{\includegraphics[width=.8\textwidth]{fig/sysmon-wr-fsm}}
\caption{FSM states when the SysMon writes to the \textit{wb\_i2c\_bridge}}
\label{fig:sysmon-wr-fsm}
\end{figure}
......@@ -424,15 +415,17 @@ the SysMon after the \textit{writereg} or \textit{writemregs} has been completed
\label{fig:sysmon-rd-fsm}
\end{figure}
When the SysMon reads (Figure~\ref{fig:sysmon-rd-fsm}), the first few
steps are the same as for a write. The address is shifted in and checked in the
Wishbone transfer simulation state. In the case of a SysMon reading from a board,
When the SysMon reads (Figure~\ref{fig:sysmon-rd-fsm}), the address is shifted in
as in the case of a write. In the case of a SysMon reading from a board,
however, the I$^2$C transfer is restarted and the order is reversed (SysMon starts
reading). Thus, while in \textit{OPER}, the FSM detects a high value on \textit{op\_o}
corresponding to an I$^2$C read transfer, and goes into the \textit{SYSMON\_RD\_WB}
state. The value of the register is read while in this state, and sent via I$^2$C
in the \textit{SYSMON\_RD} state.
Note that on an error in any Wishbone transfer, the FSM goes back to the \textit{IDLE}
state, setting the \textit{err\_p\_o} output for one \textit{clk\_i} cycle.
The design also contains an FSM watchdog component, which resets the main FSM
in case of errors in communication. The watchdog timeout value is configured
via the \textit{g\_wdt\_max} generic and can be calculated as outlined in
......@@ -455,9 +448,9 @@ on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}.
\hline
\multicolumn{1}{c}{\textbf{Resource}} & \textbf{Used} & \textbf{Available} & \textbf{\%} \\
\hline
Slices & 76 & 6822 & 1.1 \\
Slice registers & 172 & 54576 & 0.3 \\
LUTs & 151 & 27288 & 0.6 \\
Slices & 94 & 6822 & 1.3 \\
Slice registers & 168 & 54576 & 0.3 \\
LUTs & 188 & 27288 & 0.6 \\
\hline
\end{tabular}
}
......
modules/common/gc_i2c_slave.vhd
View file @ c63535f0
......@@ -126,7 +126,6 @@ architecture behav of gc_i2c_slave is
(
IDLE, -- idle
ADDR, -- shift in I2C address bits
ADDR_CHECK, -- check received I2C address
ADDR_ACK, -- ACK/NACK to I2C address
RD, -- shift in byte to read
RD_ACK, -- ACK/NACK to received byte
......@@ -282,7 +281,7 @@ begin
rxsr <= (others => '0');
txsr <= (others => '0');
mst_acked <= '0';
sda_en_o <= '0';
sda_en_o <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
......@@ -323,31 +322,30 @@ begin
bit_cnt <= bit_cnt + 1;
end if;
--
-- Checking the bit counter is done on the falling edge of SCL
--
-- If 8 bits have been shifted in, the received address is checked
-- and the slave goes in the ADDR_ACK state.
--
-- If the address is not ours, go back to IDLE and set inhibit bits
-- so bytes sent to or received from another slave that happen to
-- coincide to the address of this slave don't get interpreted
-- as accesses to this slave.
--
if (scl_f_edge_p = '1') then
-- If we've shifted in 8 bits, go to ADDR_CHECK
if (bit_cnt = 0) then
state <= ADDR_CHECK;
if (rxsr(7 downto 1) = i2c_addr_i) then
op_o <= rxsr(0);
addr_good_p_o <= '1';
state <= ADDR_ACK;
else
inhibit <= '1';
state <= IDLE;
end if;
end if;
end if;
---------------------------------------------------------------------
-- ADDR_CHECK
---------------------------------------------------------------------
when ADDR_CHECK =>
-- if the address is ours, set the OP output and go to ACK state
if (rxsr(7 downto 1) = i2c_addr_i) then
op_o <= rxsr(0);
addr_good_p_o <= '1';
state <= ADDR_ACK;
-- if the address is not ours, the FSM should be inhibited so a
-- byte sent to another slave doesn't get interpreted as this
-- slave's address
else
inhibit <= '1';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- ADDR_ACK
---------------------------------------------------------------------
......@@ -355,13 +353,18 @@ begin
-- clear addr_good pulse
addr_good_p_o <= '0';
-- send ACK from input and go start reading or writing based on OP
-- send ACK from input, check the ACK on falling edge and go to
-- loading of the TXSR if the OP bit is a write, or read otherwise
sda_en_o <= ack_i;
if (scl_f_edge_p = '1') then
if (rxsr(0) = '0') then
state <= RD;
if (ack_i = '1') then
if (rxsr(0) = '0') then
state <= RD;
else
state <= WR_LOAD_TXSR;
end if;
else
state <= WR_LOAD_TXSR;
state <= IDLE;
end if;
end if;
......
modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
View file @ c63535f0
......@@ -114,7 +114,6 @@ architecture behav of wb_i2c_bridge is
(
IDLE, -- idle state
SYSMON_WB_ADR, -- get the WB register address
SIM_WB_TRANSF, -- simulate a WB transfer with the received address
OPER, -- operation to perform on the WB register
SYSMON_RD_WB, -- perform a WB read transfer, for sending word to the SysMon
SYSMON_RD, -- send the word to the SysMon during read transfer
......@@ -274,36 +273,12 @@ begin
when SYSMON_WB_ADR =>
if (slv_r_done_p = '1') then
wb_adr <= wb_adr(7 downto 0) & rx_byte;
slv_ack <= '1';
adr_byte_cnt <= adr_byte_cnt + 1;
if (adr_byte_cnt = 1) then
state <= SIM_WB_TRANSF;
state <= OPER;
end if;
end if;
---------------------------------------------------------------------
-- SIM_WB_TRANSF
---------------------------------------------------------------------
-- Simulate a Wishbone transfer with the received address and go
-- to operation state if we get a WB ACK, or back to idle if we get
-- a WB error. In the latter case, an NACK is sent to the SysMon.
---------------------------------------------------------------------
when SIM_WB_TRANSF =>
wb_cyc <= '1';
wb_stb <= '1';
if (wb_ack = '1') then
slv_ack <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= OPER;
elsif (wb_err = '1') then
err_p_o <= '1';
slv_ack <= '0';
wb_cyc <= '0';
wb_stb <= '0';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- OPER
---------------------------------------------------------------------
......@@ -324,11 +299,9 @@ begin
if (slv_r_done_p = '1') then
wb_dat_out <= rx_byte & wb_dat_out(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
slv_ack <= '1';
state <= SYSMON_WR;
elsif (slv_addr_good_p = '1') and (op = '1') then
slv_ack <= '1';
state <= SYSMON_RD_WB;
state <= SYSMON_RD_WB;
end if;
---------------------------------------------------------------------
......@@ -342,12 +315,9 @@ begin
if (slv_r_done_p = '1') then
wb_dat_out <= rx_byte & wb_dat_out(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
slv_ack <= '1';
if (dat_byte_cnt = 3) then
state <= SYSMON_WR_WB;
state <= SYSMON_WR_WB;
end if;
-- elsif (slv_sto_p = '1') then
-- state <= IDLE;
end if;
---------------------------------------------------------------------
......@@ -360,11 +330,11 @@ begin
wb_cyc <= '1';
wb_stb <= '1';
wb_we <= '1';
if (wb_ack = '1') then -- or (wb_err = '1') then
if (wb_ack = '1') then
wb_cyc <= '0';
wb_stb <= '0';
wb_we <= '0';
state <= SYSMON_WR; --IDLE;
state <= SYSMON_WR;
elsif (wb_err = '1') then
err_p_o <= '1';
state <= IDLE;
......@@ -402,12 +372,9 @@ begin
if (slv_w_done_p = '1') then
wb_dat_in <= x"00" & wb_dat_in(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
slv_ack <= '1';
if (dat_byte_cnt = 3) then
state <= IDLE;
end if;
-- elsif (slv_sto_p = '1') then
-- state <= IDLE;
end if;
---------------------------------------------------------------------
......
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