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Commit f9b70d78 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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genrams: fix typo in inferred async fifos

parent b60dd256
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modules/genrams/common/inferred_async_fifo.vhd
+ 1
− 1
View file @ f9b70d78
......@@ -252,7 +252,7 @@ begin -- syn
p_gen_going_full : process(we_int, wcb, rcb)
begin
if ((wcb.bin (wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
and (wcb.bin(wcb.bin'left) /= rcb.bin_x(wcb.bin_x'left))) then
and (wcb.bin(wcb.bin'left) /= rcb.bin_x(rcb.bin_x'left))) then
going_full <= '1';
elsif (we_int = '1'
and (wcb.bin_next(wcb.bin'left-1 downto 0) = rcb.bin_x(rcb.bin_x'left-1 downto 0))
......
modules/genrams/common/inferred_async_fifo_dual_rst.vhd
+ 1
− 1
View file @ f9b70d78
......@@ -223,7 +223,7 @@ begin -- syn
p_gen_going_full : process(rcb, wcb, we_int)
begin
if ((wcb.bin (wcb.bin'LEFT-1 downto 0) = rcb.bin_x(rcb.bin_x'LEFT-1 downto 0))
and (wcb.bin(wcb.bin'LEFT) /= rcb.bin_x(wcb.bin_x'LEFT))) then
and (wcb.bin(wcb.bin'LEFT) /= rcb.bin_x(rcb.bin_x'LEFT))) then
going_full <= '1';
elsif (we_int = '1'
and (wcb.bin_next(wcb.bin'LEFT-1 downto 0) = rcb.bin_x(rcb.bin_x'LEFT-1 downto 0))
......
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