If a very fast WB master queues a single-byte SPI command followed
immediately by the execute instruction, the SPI command will use
the old data in the FIFO. This delays execution by 1 cycle.

It was causing the simulation to fail with designs containing a xwb_register_link component.

Use a counter instead of a shift register + comparator.

It is based on gc_glitch_filt, but with the glitch filter length
dynamically progammable via a port.

Using the volatile configuration register to configure a flash chip
is a bad idea. The problem is that if the FPGA is reset, the flash
may be in a state inconsistent with what the FPGA requires to boot.

The correct solution is to configure the non-volatile configuration
register on the chip to what the FPGA expects on power-on. Then use
these same settings inside the flash core.

Going this route makes it necessary for software to be able to set
the non-volatile configuration register. Rather than making the core
even more complicated than it is, I have elected to add a FIFO which
software can fill to issue custom SPI commands. Since erase can only
be done from software anyway, I removed this code and let erase use
the custom command FIFO.

Comparing std_logic <= '0' seems to work!
However, it is certainly not what the author intended.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

This is done by adding a generic to the entity, which is connected directly to
the gc_fsm_watchdog component instantiated within the wb_i2c_bridge. The user
should calculate the appropriate watchdog timeout value and set it via this
generic.

The instantiation template in the wishbone_pkg is also updated.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

To make the design more modular, moved the synchronization chain out of
the gc_glitch_filt component. Made the necessary changes in the
components using the gc_glitch_filt.

Also added gc_glitch_filt documentation.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Grzegorz Daniluk authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Xilinx defines almost full threshold not as the used words in the FIFO but as
number of available empty words (UG363 - Virtex 6 FPGA Memory Resources

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Also updated the rest of the documentation file to have a pretty
regmap.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Miguel Jimenez Lopez authored 11 years ago and Grzegorz Daniluk committed 11 years ago

This change is necessary for network control/monitor tool in order to read the GUI command output.
The GUI command output can not be stored into a 1024 bytes fifo.

wb_irq_slave: added clear and enable registers

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- I2C slave component now samples SDA line one rising SCL and changes
states and shifts out bits on its falling edge
- I2C slave component has clearer status outputs
- bridge component changed to reflect changes in I2C slave interface
- bridge component also returns to IDLE state on I2C stop condition, as
reflected by the I2C slave

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- an FSM watchdog component was added to the multiboot_fsm; the timeout of
the wathcdog is reflected in the component's status register
- multiboot_regs was wbgen-ized
- updated wb_xil_multiboot top-level to reflect new changes

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>