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Commit ae79f336 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'master' into proposed_master

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doc/Makefile
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......@@ -43,6 +43,9 @@ MAKEINFO ?= makeinfo
all: images $(ALL)
$(MAKE) terse
$(MAKE) -C gc_i2c_slave
$(MAKE) -C wb_i2c_bridge
$(MAKE) -C wb_xil_multiboot
images::
if [ -d images ]; then $(MAKE) -C images || exit 1; fi
......
doc/gc_fsm_watchdog/Makefile 0 → 100644
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FILE=gc_fsm_watchdog
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
# bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
doc/gc_fsm_watchdog/README.txt 0 → 100644
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Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape
\ No newline at end of file
doc/gc_fsm_watchdog/cern-title.tex 0 → 100644
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\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{Finite State Machine Watchdog Timer}}
\noindent \rule{\textwidth}{.1cm}
\hfill November 23, 2013
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
doc/gc_fsm_watchdog/fig/Makefile 0 → 100644
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SRC = $(wildcard *.svg)
OBJS = $(SRC:.svg=.pdf)
all: $(OBJS)
%.pdf : %.svg
inkscape -f $< -A $@
clean :
rm -f *.pdf
doc/gc_fsm_watchdog/fig/cern-logo.svg 0 → 100644
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@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
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%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{color}
\usepackage[toc,page]{appendix}
% Header and footer customization
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
23-11-2013 & 0.1 & First draft \\
\hline
\end{tabular}
}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables
\section*{List of Abbreviations}
\begin{tabular}{l l}
FSM & Finite State Machine \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
%==============================================================================
% SEC: Intro
%==============================================================================
\section{Introduction}
\label{sec:intro}
The Finite State Machine (FSM) Watchdog Timer component (\textit{gc\_fsm\_watchdog})
is a simple component that can be used to reset an FSM in case it spends too much
time outside the state machine's IDLE state. The component asserts its output signal
when the watchdog reaches a user-selected value. This output can then be used
in the HDL code to reset the FSM.
%==============================================================================
% SEC: Instantiation
%==============================================================================
\section{Instantiation}
\label{sec:instantiation}
The ports of the \textit{gc\_fsm\_watchdog} module are shown in Table~\ref{tbl:ports}.
\begin{table}[h]
\caption{Ports of \textit{vbcp\_wb} module}
\label{tbl:ports}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Port}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
clk\_i & 1 & Clock input \\
rst\_n\_i & 1 & Active-low reset input \\
wdt\_rst\_i & 1 & Active-high reset input from the FSM to the watchdog timer \newline
Synchronous to \textit{clk\_i}\\
fsm\_rst\_o & 1 & Active-high reset output from the watchdog timer to the FSM \newline
Synchronous to \textit{clk\_i}\\ \\
\hline
\end{tabular}
}
\end{table}
Figure~\ref{fig:conn} shows how the \textit{gc\_fsm\_watchdog} module can be connected
to an FSM in a design. The clock (\textit{clk\_i}) and active-low reset (\textit{rst\_n\_i})
input ports should be connected to the master reset lines in the design. The signal connected
to the active-high input reset port (\textit{wdt\_rst\_i}) should be asserted by the FSM when
it is in its IDLE state. The reset output to the FSM (\textit{fsm\_rst\_o}) should be
ORed together with the active-low master reset input and connected to the reset input
of the FSM.
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/conn}}
\caption{Connecting the \textit{gc\_fsm\_watchdog} module to an FSM}
\label{fig:conn}
\end{figure}
Examples of how to connect to the \textit{gc\_fsm\_watchdog} module are given in
Appendix~\ref{app:instantiation}.
%==============================================================================
% SEC: Instantiation
%==============================================================================
\section{Implementation}
\label{sec:implem}
The watchdog timer is implemented as a simple up-counter which asserts the
\textit{fsm\_rst\_o} output when the maximum value of \textit{g\_wdt\_max} is
reached. The counter is reset by either the active-low (system) reset and the
active-high (FSM) reset. A diagram of the block is shown in Figure~\ref{fig:implem}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/implem}}
\caption{Diagram of the FSM watchdog module}
\label{fig:implem}
\end{figure}
%==============================================================================
% APPENDICES
%==============================================================================
\pagebreak
\begin{appendices}
\section{Example instantiation}
\label{app:instantiation}
\subsection{VHDL}
\begin{verbatim}
p_proc : process (sys_clk)
begin
if rising_edge(sys_clk) then
if (sys_rst_n = '0') or (rst_fr_wdt = '1') then
state <= IDLE;
else
case state is
when IDLE =>
wdt_rst <= '1';
if (trigger = '1') then
wdt_rst <= '0';
state <= NEXT_STATE;
end if;
when NEXT_STATE =>
-- ...
end case;
end if;
end if;
end process p_proc;
cmp_fsm_watchdog : gc_fsm_watchdog
generic map
(
-- FSM should return to IDLE within 256 clk_i cycles
g_wdt_max => 256
)
port map
(
clk_i => sys_clk;
rst_n_i => sys_rst_n;
wdt_rst_i => wdt_rst;
fsm_rst_o => fsm_rst;
);
\end{verbatim}
\pagebreak
\subsection{Verilog}
\begin{verbatim}
always @(posedge sys_clk)
begin
if (!rst_n_i) or (rst_fr_wdt) then
state <= IDLE;
else
begin
case (state)
IDLE:
begin
wdt_rst <= 1'b1;
if (trigger = '1') then
begin
wdt_rst <= 1'b0;
state <= NEXT_STATE;
end
end
NEXT_STATE:
begin
// ...
end
endcase
end
end
gc_fsm_watchdog cmp_gc_fsm_watchdog (
.clk_i (sys_clk),
.rst_n_i (sys_rst_n),
.wdt_rst_i (wdt_rst),
.fsm_rst_o (rst_fr_wdt)
)
\end{verbatim}
\end{appendices}
%==============================================================================
% Bibliography
%==============================================================================
%\pagebreak
%\bibliographystyle{ieeetr}
%\bibliography{gc_fsm_watchdog}
\end{document}
\ No newline at end of file
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FILE=gc_glitch_filt
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
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Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape
\ No newline at end of file
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\begin{titlepage}
\vspace*{3cm}
\noindent{\LARGE \textbf{Glitch filter}}
\noindent \rule{\textwidth}{.1cm}
\hfill March 3, 2014
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
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SRC = $(wildcard *.svg)
OBJS = $(SRC:.svg=.pdf)
all: $(OBJS)
echo $(OBJS)
%.pdf : %.svg
inkscape -f $< -A $@
clean :
rm -f *.pdf
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@misc{ohwr,
title = {{Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/}}
}
@misc{gencores-ohwr,
title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
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%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames]{color}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
\usepackage{graphicx}
\usepackage{rotating}
\usepackage{multirow}
\usepackage{longtable}
% Header and footer customization
\usepackage{fancyhdr}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
03-03-2014 & 0.01 & First draft \\
\hline
\end{tabular}
}
%------------------------------------------------------------------------------
% Generate TOC and pagebreak after it
%------------------------------------------------------------------------------
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\listoffigures
\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
FF & Flip-Flop \\
\end{tabular}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\section{Introduction}
\label{sec:intro}
This document presents the \textit{gc\_glitch\_filt} component, a modular glitch
filter open-hardware~\cite{ohwr} design for FPGA or ASIC implementation. It is
implemented as one short VHDL file which can be found under the following folder
of the \textit{general-cores} repository~\cite{gencores-ohwr}:
\begin{itemize}
\item \textit{modules/common/}
\end{itemize}
%==============================================================================
% SEC: Instantiation
%==============================================================================
\section{Instantiation}
\label{sec:instantiation}
Table~\ref{tbl:ports} shows the instantiation template for the \textit{gc\_glitch\_filt}
component. It can be directly instantiated in a VHDL or Verilog design.
The data to be filtered should be connected to the \textit{dat\_i} input. Note that
the data is not synchronized internally to the \textit{clk\_i} signal, if metastability
is a concern, a synchronization chain should be provided outside the component.
The deglitched data is presented at the \textit{dat\_o} output a number of \textit{g\_len+1}
clock cycles later.
\begin{table}[h]
\caption{Ports and generics of \textit{gc\_i2c\_slave} module}
\label{tbl:ports}
\centerline
{
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
g\_len & Glitch filter length generic (in \textit{clk\_i} cycles) \newline
1 -- glitches narrower than 1 \textit{clk\_i} cycle are filtered \newline
2 -- glitches narrower than 2 \textit{clk\_i} cycles are filtered \newline
etc.\\
clk\_i & Clock input \\
rst\_n\_i & Active-low reset input \\
dat\_i & Data input (should be synchronous to \textit{clk\_i})\\
dat\_o & Deglitched data output (synchronous to \textit{clk\_i}) \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: implem
%==============================================================================
\pagebreak
\section{Implementation and operation}
Figure~\ref{fig:implem} shows the implementation of the \textit{gc\_glitch\_filt}
block.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/implem}}
\caption{Implementation of the \textit{gc\_glitch\_filt} block}
\label{fig:implem}
\end{figure}
The block's operation is very simple and can be summarized as follows. At synthesis
time, \textit{g\_len} FFs are generated. If the \textit{dat\_i} is stable for a number
of \textit{g\_len} cycles, all FFs in the deglitching stage have the same value,
and the \textit{dat\_o} output changes to reflect the state of \textit{dat\_i}.
Should a glitch occur at any time on the \textit{dat\_i} signal, it is filtered
by the AND (or NAND) gate at the output.
All the FFs are cleared ('0') on reset.
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{gc_glitch_filt}
\end{document}
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