Made I2C slave and bridge work properly
- I2C slave component now samples SDA line one rising SCL and changes states and shifts out bits on its falling edge - I2C slave component has clearer status outputs - bridge component changed to reflect changes in I2C slave interface - bridge component also returns to IDLE state on I2C stop condition, as reflected by the I2C slave Signed-off-by:Theodor Stana <t.stana@cern.ch> Signed-off-by:
Tomasz Włostowski <tomasz.wlostowski@cern.ch>
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- modules/common/gc_glitch_filt.vhd 6 additions, 25 deletionsmodules/common/gc_glitch_filt.vhd
- modules/common/gc_i2c_slave.vhd 179 additions, 207 deletionsmodules/common/gc_i2c_slave.vhd
- modules/common/gencores_pkg.vhd 71 additions, 42 deletionsmodules/common/gencores_pkg.vhd
- modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd 170 additions, 133 deletionsmodules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
- modules/wishbone/wishbone_pkg.vhd 17 additions, 11 deletionsmodules/wishbone/wishbone_pkg.vhd
- sim/wb_i2c_bridge/i2c_bus_model.vhd 89 additions, 0 deletionssim/wb_i2c_bridge/i2c_bus_model.vhd
- sim/wb_i2c_bridge/i2c_master_bit_ctrl.vhd 576 additions, 0 deletionssim/wb_i2c_bridge/i2c_master_bit_ctrl.vhd
- sim/wb_i2c_bridge/i2c_master_byte_ctrl.vhd 368 additions, 0 deletionssim/wb_i2c_bridge/i2c_master_byte_ctrl.vhd
- sim/wb_i2c_bridge/run.do 30 additions, 0 deletionssim/wb_i2c_bridge/run.do
- sim/wb_i2c_bridge/tb_gc_i2c_slave.vhd 505 additions, 0 deletionssim/wb_i2c_bridge/tb_gc_i2c_slave.vhd
- sim/wb_i2c_bridge/tb_wb_i2c_bridge.vhd 698 additions, 0 deletionssim/wb_i2c_bridge/tb_wb_i2c_bridge.vhd
- sim/wb_i2c_bridge/wave-i2cs.do 64 additions, 0 deletionssim/wb_i2c_bridge/wave-i2cs.do
- sim/wb_i2c_bridge/wave.do 32 additions, 0 deletionssim/wb_i2c_bridge/wave.do
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