gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;

Use a counter instead of a shift register + comparator.

It is based on gc_glitch_filt, but with the glitch filter length
dynamically progammable via a port.

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- I2C slave component now samples SDA line one rising SCL and changes
states and shifts out bits on its falling edge
- I2C slave component has clearer status outputs
- bridge component changed to reflect changes in I2C slave interface
- bridge component also returns to IDLE state on I2C stop condition, as
reflected by the I2C slave

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

- gc_i2c_slave     -- generic I2C slave to be used with a processor or tied to a
                      Wishbone interface
- gc_glitch_filter -- glitch filter with selectable number of taps
- wb_i2c_bridge    -- I2C bridge implementing the protocol defined with ELMA
                      for monitoring VME crates
- wb_xil_multiboot -- module that accesses the Spartan-6 configuration logic
                      for reconfiguring the FPGA using MultiBoot

Doc files for each of these modules can be found in the doc/ folder.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

common/gc_crc_gen: fixed reverse_range bug causing invalid CRCs, added restart input and combinatorial output to reduce latency

Conflicts:

	modules/common/gc_crc_gen.vhd

Conflicts:

	modules/common/Manifest.py
	modules/common/gencores_pkg.vhd

Each clock domain needs a separate reset line.
However, one cannot reset only a single domain---that could cause inconsistency
at clock crossing boundaries.
This change splits reset lines per clock domain and centralizes generation.

Updated uses of the wishbone_pkg to use Tom's naming conventions.
Added Manifests for the new files.