This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is beneficial because the gc_sync_ffs has a Xilinx "keep" attribute, which prevents the tools
from trimming out unused logic, even when the user has set the relevant generics to "FALSE".

The previous implementation was introducing latches to the GN4124 core under Xilinx ISE.

Tested and verified to work with the following SPEC-based reference designs:
 - WR
 - MT
 - WRTD

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.