[hdl] use KEEP_HIERARCHY for cross-clock domain modules

This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>