This is to avoid any confusion caused by g_SYNC_EDGE and g_EDGE
generics used in gc_sync, gc_sync_ffs and gc_sync_edge modules.

Also use capitals for generics as defined by our coding style.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Also perform cleanup of sync and edge modules.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Jan Pospisil authored 8 years ago and Dimitris Lampridis committed 8 years ago

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;